mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 18:29:45 +00:00
Pull the VECTOR_SHUFFLE and BUILD_VECTOR lowering code out into separate
functions, which makes the code much cleaner :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27692 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
0fa07f95b6
commit
f1b4708950
@ -587,11 +587,166 @@ static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2],
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return false;
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}
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// If this is a case we can't handle, return null and let the default
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// expansion code take care of it. If we CAN select this case, and if it
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// selects to a single instruction, return Op. Otherwise, if we can codegen
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// this case more efficiently than a constant pool load, lower it to the
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// sequence of ops that should be used.
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static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
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// If this is a vector of constants or undefs, get the bits. A bit in
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// UndefBits is set if the corresponding element of the vector is an
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// ISD::UNDEF value. For undefs, the corresponding VectorBits values are
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// zero.
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uint64_t VectorBits[2];
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uint64_t UndefBits[2];
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if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits))
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return SDOperand(); // Not a constant vector.
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// See if this is all zeros.
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if ((VectorBits[0] | VectorBits[1]) == 0) {
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// Canonicalize all zero vectors to be v4i32.
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if (Op.getValueType() != MVT::v4i32) {
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SDOperand Z = DAG.getConstant(0, MVT::i32);
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Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z);
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Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z);
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}
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return Op;
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}
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// Check to see if this is something we can use VSPLTI* to form.
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MVT::ValueType CanonicalVT = MVT::Other;
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SDNode *CST = 0;
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if ((CST = PPC::get_VSPLTI_elt(Op.Val, 4, DAG).Val)) // vspltisw
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CanonicalVT = MVT::v4i32;
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else if ((CST = PPC::get_VSPLTI_elt(Op.Val, 2, DAG).Val)) // vspltish
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CanonicalVT = MVT::v8i16;
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else if ((CST = PPC::get_VSPLTI_elt(Op.Val, 1, DAG).Val)) // vspltisb
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CanonicalVT = MVT::v16i8;
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// If this matches one of the vsplti* patterns, force it to the canonical
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// type for the pattern.
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if (CST) {
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if (Op.getValueType() != CanonicalVT) {
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// Convert the splatted element to the right element type.
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SDOperand Elt = DAG.getNode(ISD::TRUNCATE,
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MVT::getVectorBaseType(CanonicalVT),
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SDOperand(CST, 0));
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std::vector<SDOperand> Ops(MVT::getVectorNumElements(CanonicalVT), Elt);
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SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT, Ops);
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Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
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}
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return Op;
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}
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// If this is some other splat of 4-byte elements, see if we can handle it
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// in another way.
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// FIXME: Make this more undef happy and work with other widths (1,2 bytes).
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if (VectorBits[0] == VectorBits[1] &&
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unsigned(VectorBits[0]) == unsigned(VectorBits[0] >> 32)) {
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unsigned Bits = unsigned(VectorBits[0]);
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// If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
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// 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). These are important
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// for fneg/fabs.
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if (Bits == 0x80000000 || Bits == 0x7FFFFFFF) {
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// Make -1 and vspltisw -1:
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SDOperand OnesI = DAG.getConstant(~0U, MVT::i32);
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SDOperand OnesV = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32,
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OnesI, OnesI, OnesI, OnesI);
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// Make the VSLW intrinsic, computing 0x8000_0000.
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SDOperand Res
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= DAG.getNode(ISD::INTRINSIC_WO_CHAIN, MVT::v4i32,
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DAG.getConstant(Intrinsic::ppc_altivec_vslw, MVT::i32),
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OnesV, OnesV);
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// If this is 0x7FFF_FFFF, xor by OnesV to invert it.
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if (Bits == 0x7FFFFFFF)
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Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV);
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return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
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}
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}
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return SDOperand();
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}
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/// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
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/// is a shuffle we can handle in a single instruction, return it. Otherwise,
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/// return the code it can be lowered into. Worst case, it can always be
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/// lowered into a vperm.
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static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
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SDOperand V1 = Op.getOperand(0);
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SDOperand V2 = Op.getOperand(1);
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SDOperand PermMask = Op.getOperand(2);
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// Cases that are handled by instructions that take permute immediates
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// (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
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// selected by the instruction selector.
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if (V2.getOpcode() == ISD::UNDEF) {
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if (PPC::isSplatShuffleMask(PermMask.Val, 1) ||
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PPC::isSplatShuffleMask(PermMask.Val, 2) ||
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PPC::isSplatShuffleMask(PermMask.Val, 4) ||
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PPC::isVPKUWUMShuffleMask(PermMask.Val, true) ||
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PPC::isVPKUHUMShuffleMask(PermMask.Val, true) ||
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PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 ||
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PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) ||
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PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) ||
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PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) ||
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PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) ||
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PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) ||
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PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) {
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return Op;
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}
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}
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// Altivec has a variety of "shuffle immediates" that take two vector inputs
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// and produce a fixed permutation. If any of these match, do not lower to
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// VPERM.
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if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) ||
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PPC::isVPKUHUMShuffleMask(PermMask.Val, false) ||
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PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 ||
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PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) ||
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PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) ||
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PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) ||
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PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) ||
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PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) ||
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PPC::isVMRGHShuffleMask(PermMask.Val, 4, false))
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return Op;
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// TODO: Handle more cases, and also handle cases that are cheaper to do as
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// multiple such instructions than as a constant pool load/vperm pair.
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// Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
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// vector that will get spilled to the constant pool.
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if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
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// The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
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// that it is in input element units, not in bytes. Convert now.
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MVT::ValueType EltVT = MVT::getVectorBaseType(V1.getValueType());
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unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8;
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std::vector<SDOperand> ResultMask;
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for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
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unsigned SrcElt =cast<ConstantSDNode>(PermMask.getOperand(i))->getValue();
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for (unsigned j = 0; j != BytesPerElement; ++j)
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ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
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MVT::i8));
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}
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SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, ResultMask);
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return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
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}
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/// LowerOperation - Provide custom lowering hooks for some operations.
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///
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SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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switch (Op.getOpcode()) {
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default: assert(0 && "Wasn't expecting to be able to lower this!");
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case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
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case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
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case ISD::FP_TO_SINT: {
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assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType()));
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SDOperand Src = Op.getOperand(0);
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@ -963,153 +1118,6 @@ SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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// Load it out.
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return DAG.getLoad(Op.getValueType(), Store, FIdx, DAG.getSrcValue(NULL));
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}
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case ISD::BUILD_VECTOR: {
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// If this is a case we can't handle, return null and let the default
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// expansion code take care of it. If we CAN select this case, return Op
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// or something simpler.
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// If this is a vector of constants or undefs, get the bits. A bit in
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// UndefBits is set if the corresponding element of the vector is an
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// ISD::UNDEF value. For undefs, the corresponding VectorBits values are
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// zero.
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uint64_t VectorBits[2];
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uint64_t UndefBits[2];
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if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits))
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return SDOperand(); // Not a constant vector.
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// See if this is all zeros.
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if ((VectorBits[0] | VectorBits[1]) == 0) {
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// Canonicalize all zero vectors to be v4i32.
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if (Op.getValueType() != MVT::v4i32) {
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SDOperand Z = DAG.getConstant(0, MVT::i32);
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Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z);
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Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z);
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}
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return Op;
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}
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// Check to see if this is something we can use VSPLTI* to form.
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MVT::ValueType CanonicalVT = MVT::Other;
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SDNode *CST = 0;
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if ((CST = PPC::get_VSPLTI_elt(Op.Val, 4, DAG).Val)) // vspltisw
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CanonicalVT = MVT::v4i32;
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else if ((CST = PPC::get_VSPLTI_elt(Op.Val, 2, DAG).Val)) // vspltish
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CanonicalVT = MVT::v8i16;
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else if ((CST = PPC::get_VSPLTI_elt(Op.Val, 1, DAG).Val)) // vspltisb
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CanonicalVT = MVT::v16i8;
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// If this matches one of the vsplti* patterns, force it to the canonical
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// type for the pattern.
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if (CST) {
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if (Op.getValueType() != CanonicalVT) {
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// Convert the splatted element to the right element type.
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SDOperand Elt = DAG.getNode(ISD::TRUNCATE,
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MVT::getVectorBaseType(CanonicalVT),
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SDOperand(CST, 0));
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std::vector<SDOperand> Ops(MVT::getVectorNumElements(CanonicalVT), Elt);
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SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT, Ops);
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Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
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}
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return Op;
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}
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// If this is some other splat of 4-byte elements, see if we can handle it
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// in another way.
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// FIXME: Make this more undef happy and work with other widths (1,2 bytes).
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if (VectorBits[0] == VectorBits[1] &&
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unsigned(VectorBits[0]) == unsigned(VectorBits[0] >> 32)) {
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unsigned Bits = unsigned(VectorBits[0]);
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// If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
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// 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). These are important
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// for fneg/fabs.
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if (Bits == 0x80000000 || Bits == 0x7FFFFFFF) {
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// Make -1 and vspltisw -1:
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SDOperand OnesI = DAG.getConstant(~0U, MVT::i32);
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SDOperand OnesV = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32,
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OnesI, OnesI, OnesI, OnesI);
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// Make the VSLW intrinsic, computing 0x8000_0000.
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SDOperand Res
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= DAG.getNode(ISD::INTRINSIC_WO_CHAIN, MVT::v4i32,
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DAG.getConstant(Intrinsic::ppc_altivec_vslw, MVT::i32),
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OnesV, OnesV);
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// If this is 0x7FFF_FFFF, xor by OnesV to invert it.
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if (Bits == 0x7FFFFFFF)
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Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV);
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return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
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}
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}
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return SDOperand();
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}
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case ISD::VECTOR_SHUFFLE: {
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SDOperand V1 = Op.getOperand(0);
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SDOperand V2 = Op.getOperand(1);
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SDOperand PermMask = Op.getOperand(2);
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// Cases that are handled by instructions that take permute immediates
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// (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
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// selected by the instruction selector.
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if (V2.getOpcode() == ISD::UNDEF) {
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if (PPC::isSplatShuffleMask(PermMask.Val, 1) ||
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PPC::isSplatShuffleMask(PermMask.Val, 2) ||
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PPC::isSplatShuffleMask(PermMask.Val, 4) ||
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PPC::isVPKUWUMShuffleMask(PermMask.Val, true) ||
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PPC::isVPKUHUMShuffleMask(PermMask.Val, true) ||
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PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 ||
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PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) ||
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PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) ||
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PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) ||
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PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) ||
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PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) ||
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PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) {
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return Op;
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}
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}
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// Altivec has a variety of "shuffle immediates" that take two vector inputs
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// and produce a fixed permutation. If any of these match, do not lower to
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// VPERM.
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if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) ||
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PPC::isVPKUHUMShuffleMask(PermMask.Val, false) ||
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PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 ||
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PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) ||
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PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) ||
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PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) ||
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PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) ||
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PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) ||
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PPC::isVMRGHShuffleMask(PermMask.Val, 4, false))
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return Op;
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// TODO: Handle more cases, and also handle cases that are cheaper to do as
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// multiple such instructions than as a constant pool load/vperm pair.
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// Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
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// vector that will get spilled to the constant pool.
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if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
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// The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
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// that it is in input element units, not in bytes. Convert now.
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MVT::ValueType EltVT = MVT::getVectorBaseType(V1.getValueType());
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unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8;
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std::vector<SDOperand> ResultMask;
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for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
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unsigned SrcElt =cast<ConstantSDNode>(PermMask.getOperand(i))->getValue();
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for (unsigned j = 0; j != BytesPerElement; ++j)
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ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
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MVT::i8));
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}
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SDOperand VPermMask =DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, ResultMask);
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return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
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}
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case ISD::INTRINSIC_WO_CHAIN: {
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unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue();
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