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[AArch64] Robustize neon-scalar-copy.ll tests. NFC.

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Some of those didn't even have run lines: they were removed
inadvertently during the Great Merge of 2014.

They used to check for DUPs, but now we go through W-regs?
Filed PR22418 for that potential regression.

For now, just make the tests explicit, so we now where we stand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227635 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ahmed Bougacha 2015-01-30 23:13:57 +00:00
parent cbae08dc4d
commit f2045fb1f2
1 changed files with 59 additions and 39 deletions
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98
test/CodeGen/AArch64/neon-scalar-copy.ll
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@ -1,101 +1,119 @@
; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s --check-prefix=CHECK
; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon -asm-verbose=false < %s | FileCheck %s
define float @test_dup_sv2S(<2 x float> %v) {
; CHECK-LABEL: test_dup_sv2S
; CHECK: ins {{v[0-9]+}}.s[0], {{v[0-9]+}}.s[1]
define float @test_dup_sv2S(<2 x float> %v) #0 {
; CHECK-LABEL: test_dup_sv2S:
; CHECK-NEXT: ins {{v[0-9]+}}.s[0], {{v[0-9]+}}.s[1]
; CHECK-NEXT: ret
%tmp1 = extractelement <2 x float> %v, i32 1
ret float %tmp1
}
define float @test_dup_sv2S_0(<2 x float> %v) {
; CHECK-LABEL: test_dup_sv2S_0
define float @test_dup_sv2S_0(<2 x float> %v) #0 {
; CHECK-LABEL: test_dup_sv2S_0:
; CHECK-NOT: dup {{[vsd][0-9]+}}
; CHECK-NOT: ins {{[vsd][0-9]+}}
; CHECK: ret
; CHECK-NEXT: ret
%tmp1 = extractelement <2 x float> %v, i32 0
ret float %tmp1
}
define float @test_dup_sv4S(<4 x float> %v) {
; CHECK-LABEL: test_dup_sv4S
define float @test_dup_sv4S(<4 x float> %v) #0 {
; CHECK-LABEL: test_dup_sv4S:
; CHECK-NOT: dup {{[vsd][0-9]+}}
; CHECK-NOT: ins {{[vsd][0-9]+}}
; CHECK: ret
; CHECK-NEXT: ret
%tmp1 = extractelement <4 x float> %v, i32 0
ret float %tmp1
}
define double @test_dup_dvD(<1 x double> %v) {
; CHECK-LABEL: test_dup_dvD
define double @test_dup_dvD(<1 x double> %v) #0 {
; CHECK-LABEL: test_dup_dvD:
; CHECK-NOT: dup {{[vsd][0-9]+}}
; CHECK-NOT: ins {{[vsd][0-9]+}}
; CHECK: ret
; CHECK-NEXT: ret
%tmp1 = extractelement <1 x double> %v, i32 0
ret double %tmp1
}
define double @test_dup_dv2D(<2 x double> %v) {
; CHECK-LABEL: test_dup_dv2D
; CHECK: ins {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[1]
define double @test_dup_dv2D(<2 x double> %v) #0 {
; CHECK-LABEL: test_dup_dv2D:
; CHECK-NEXT: ins {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[1]
; CHECK-NEXT: ret
%tmp1 = extractelement <2 x double> %v, i32 1
ret double %tmp1
}
define double @test_dup_dv2D_0(<2 x double> %v) {
; CHECK-LABEL: test_dup_dv2D_0
; CHECK: ins {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[1]
; CHECK: ret
define double @test_dup_dv2D_0(<2 x double> %v) #0 {
; CHECK-LABEL: test_dup_dv2D_0:
; CHECK-NEXT: ins {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[1]
; CHECK-NEXT: ret
%tmp1 = extractelement <2 x double> %v, i32 1
ret double %tmp1
}
define <1 x i8> @test_vector_dup_bv16B(<16 x i8> %v1) {
; CHECK-LABEL: test_vector_dup_bv16B
define <1 x i8> @test_vector_dup_bv16B(<16 x i8> %v1) #0 {
; CHECK-LABEL: test_vector_dup_bv16B:
; CHECK-NEXT: umov [[W:w[0-9]+]], v0.b[14]
; CHECK-NEXT: fmov s0, [[W]]
; CHECK-NEXT: ret
%shuffle.i = shufflevector <16 x i8> %v1, <16 x i8> undef, <1 x i32> <i32 14>
ret <1 x i8> %shuffle.i
}
define <1 x i8> @test_vector_dup_bv8B(<8 x i8> %v1) {
; CHECK-LABEL: test_vector_dup_bv8B
define <1 x i8> @test_vector_dup_bv8B(<8 x i8> %v1) #0 {
; CHECK-LABEL: test_vector_dup_bv8B:
; CHECK-NEXT: dup v0.8b, v0.b[7]
; CHECK-NEXT: ret
%shuffle.i = shufflevector <8 x i8> %v1, <8 x i8> undef, <1 x i32> <i32 7>
ret <1 x i8> %shuffle.i
}
define <1 x i16> @test_vector_dup_hv8H(<8 x i16> %v1) {
; CHECK-LABEL: test_vector_dup_hv8H
define <1 x i16> @test_vector_dup_hv8H(<8 x i16> %v1) #0 {
; CHECK-LABEL: test_vector_dup_hv8H:
; CHECK-NEXT: umov [[W:w[0-9]+]], v0.h[7]
; CHECK-NEXT: fmov s0, [[W]]
; CHECK-NEXT: ret
%shuffle.i = shufflevector <8 x i16> %v1, <8 x i16> undef, <1 x i32> <i32 7>
ret <1 x i16> %shuffle.i
}
define <1 x i16> @test_vector_dup_hv4H(<4 x i16> %v1) {
; CHECK-LABEL: test_vector_dup_hv4H
define <1 x i16> @test_vector_dup_hv4H(<4 x i16> %v1) #0 {
; CHECK-LABEL: test_vector_dup_hv4H:
; CHECK-NEXT: dup v0.4h, v0.h[3]
; CHECK-NEXT: ret
%shuffle.i = shufflevector <4 x i16> %v1, <4 x i16> undef, <1 x i32> <i32 3>
ret <1 x i16> %shuffle.i
}
define <1 x i32> @test_vector_dup_sv4S(<4 x i32> %v1) {
; CHECK-LABEL: test_vector_dup_sv4S
define <1 x i32> @test_vector_dup_sv4S(<4 x i32> %v1) #0 {
; CHECK-LABEL: test_vector_dup_sv4S:
; CHECK-NEXT: mov [[W:w[0-9]+]], v0.s[3]
; CHECK-NEXT: fmov s0, [[W]]
; CHECK-NEXT: ret
%shuffle = shufflevector <4 x i32> %v1, <4 x i32> undef, <1 x i32> <i32 3>
ret <1 x i32> %shuffle
}
define <1 x i32> @test_vector_dup_sv2S(<2 x i32> %v1) {
; CHECK-LABEL: test_vector_dup_sv2S
define <1 x i32> @test_vector_dup_sv2S(<2 x i32> %v1) #0 {
; CHECK-LABEL: test_vector_dup_sv2S:
; CHECK-NEXT: dup v0.2s, v0.s[1]
; CHECK-NEXT: ret
%shuffle = shufflevector <2 x i32> %v1, <2 x i32> undef, <1 x i32> <i32 1>
ret <1 x i32> %shuffle
}
define <1 x i64> @test_vector_dup_dv2D(<2 x i64> %v1) {
; CHECK-LABEL: test_vector_dup_dv2D
; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #8
define <1 x i64> @test_vector_dup_dv2D(<2 x i64> %v1) #0 {
; CHECK-LABEL: test_vector_dup_dv2D:
; CHECK-NEXT: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #8
; CHECK-NEXT: ret
%shuffle.i = shufflevector <2 x i64> %v1, <2 x i64> undef, <1 x i32> <i32 1>
ret <1 x i64> %shuffle.i
}
define <1 x i64> @test_vector_copy_dup_dv2D(<1 x i64> %a, <2 x i64> %c) {
; CHECK-LABEL: test_vector_copy_dup_dv2D
; CHECK: {{dup|mov}} {{d[0-9]+}}, {{v[0-9]+}}.d[1]
define <1 x i64> @test_vector_copy_dup_dv2D(<1 x i64> %a, <2 x i64> %c) #0 {
; CHECK-LABEL: test_vector_copy_dup_dv2D:
; CHECK-NEXT: {{dup|mov}} {{d[0-9]+}}, {{v[0-9]+}}.d[1]
; CHECK-NEXT: ret
%vget_lane = extractelement <2 x i64> %c, i32 1
%vset_lane = insertelement <1 x i64> undef, i64 %vget_lane, i32 0
ret <1 x i64> %vset_lane
@ -118,3 +136,5 @@ define void @test_out_of_range_insert(<4 x i32> %vec, i32 %elt) {
insertelement <4 x i32> %vec, i32 %elt, i32 4
ret void
}
attributes #0 = { nounwind }