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Use set operations instead of plain lists to enumerate register classes.

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This simplifies many of the target description files since it is common
for register classes to be related or contain sequences of numbered
registers.

I have verified that this doesn't change the files generated by TableGen
for ARM and X86. It alters the allocation order of MBlaze GPR and Mips
FGR32 registers, but I believe the change is benign.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133105 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
2011-06-15 23:28:14 +00:00
parent f14bacc862
commit f28987b76e
15 changed files with 254 additions and 546 deletions
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lib/Target/XCore/XCoreRegisterInfo.td
+3 -3
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@@ -44,13 +44,13 @@ def LR : Ri<15, "lr">, DwarfRegNum<[15]>;
//
def GRRegs : RegisterClass<"XCore", [i32], 32,
// Return values and arguments
[R0, R1, R2, R3,
(add R0, R1, R2, R3,
// Not preserved across procedure calls
R11,
// Callee save
R4, R5, R6, R7, R8, R9, R10]>;
R4, R5, R6, R7, R8, R9, R10)>;
// Reserved
def RRegs : RegisterClass<"XCore", [i32], 32, [CP, DP, SP, LR]> {
def RRegs : RegisterClass<"XCore", [i32], 32, (add CP, DP, SP, LR)> {
let isAllocatable = 0;
}