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[Hexagon] Adding zxth instruction.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222662 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu 2014-11-24 17:11:34 +00:00
parent 9f1b025b31
commit f309d8ee65
3 changed files with 17 additions and 5 deletions
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8
lib/Target/Hexagon/HexagonInstrInfo.cpp
View File

@ -718,7 +718,7 @@ bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
case Hexagon::A2_sxtb:
case Hexagon::A2_sxth:
case Hexagon::A2_zxtb:
case Hexagon::ZXTH:
case Hexagon::A2_zxth:
return Subtarget.hasV4TOps();
}
@ -1327,6 +1327,10 @@ bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
case Hexagon::A4_pzxtbfnew:
case Hexagon::A4_pzxtbt:
case Hexagon::A4_pzxtbtnew:
case Hexagon::A4_pzxthf:
case Hexagon::A4_pzxthfnew:
case Hexagon::A4_pzxtht:
case Hexagon::A4_pzxthtnew:
case Hexagon::ADD_ri_cPt:
case Hexagon::ADD_ri_cNotPt:
case Hexagon::COMBINE_rr_cPt:
@ -1336,8 +1340,6 @@ bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
case Hexagon::ASLH_cNotPt_V4:
case Hexagon::ASRH_cPt_V4:
case Hexagon::ASRH_cNotPt_V4:
case Hexagon::ZXTH_cPt_V4:
case Hexagon::ZXTH_cNotPt_V4:
return QRI.Subtarget.hasV4TOps();
}
}

4
lib/Target/Hexagon/HexagonInstrInfo.td
View File

@ -267,6 +267,7 @@ multiclass ALU32_2op_base<string mnemonic, bits<3> minOp> {
defm sxtb : ALU32_2op_base<"sxtb", 0b101>, PredNewRel;
defm sxth : ALU32_2op_base<"sxth", 0b111>, PredNewRel;
defm zxth : ALU32_2op_base<"zxth", 0b110>, PredNewRel;
// Rd=zxtb(Rs): assembler mapped to Rd=and(Rs,#255).
// Compiler would want to generate 'zxtb' instead of 'and' becuase 'zxtb' has
@ -635,7 +636,6 @@ multiclass ALU32_2op_base2<string mnemonic> {
defm ASLH : ALU32_2op_base2<"aslh">, PredNewRel;
defm ASRH : ALU32_2op_base2<"asrh">, PredNewRel;
defm ZXTH : ALU32_2op_base2<"zxth">, PredNewRel;
def : Pat <(shl (i32 IntRegs:$src1), (i32 16)),
(ASLH IntRegs:$src1)>;
@ -2320,7 +2320,7 @@ def : Pat<(atomic_store_64 (add (i32 IntRegs:$src2), s11_3ImmPred:$offset),
// Map from r0 = and(r1, 65535) to r0 = zxth(r1)
def : Pat <(and (i32 IntRegs:$src1), 65535),
(ZXTH (i32 IntRegs:$src1))>;
(A2_zxth (i32 IntRegs:$src1))>;
// Map from r0 = and(r1, 255) to r0 = zxtb(r1).
def : Pat <(and (i32 IntRegs:$src1), 255),

10
test/MC/Hexagon/inst_zxth.ll Normal file
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@ -0,0 +1,10 @@
;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
;; RUN: | llvm-objdump -s - | FileCheck %s
define i32 @foo (i16 %a)
{
%1 = zext i16 %a to i32
ret i32 %1
}
; CHECK: 0000 0040c070 00c09f52