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Fix assert(0) conversion, as suggested by Chris.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75423 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -459,9 +459,8 @@ unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
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Reg = Candidates.find_next(Reg);
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}
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if (ScavengedReg != 0) {
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LLVM_UNREACHABLE("Scavenger slot is live, unable to scavenge another register!");
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}
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assert(ScavengedReg == 0 &&
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"Scavenger slot is live, unable to scavenge another register!");
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// Spill the scavenged register before I.
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TII->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC);
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