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Add support for 64-bit calling convention.
This is far from complete, but it is enough to make it possible to write test cases using i64 arguments. Missing features: - Floating point arguments. - Receiving arguments on the stack. - Calls. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178523 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
parent
fcb25e60f5
commit
f37812e906
@ -22,6 +22,14 @@ def RetCC_Sparc32 : CallingConv<[
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CCIfType<[f64], CCAssignToReg<[D0, D1]>>
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]>;
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// Sparc 64-bit C return-value convention.
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def RetCC_Sparc64 : CallingConv<[
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CCIfType<[i32], CCPromoteToType<i64>>,
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CCIfType<[i64], CCAssignToReg<[I0, I1, I2, I3, I4, I5]>>,
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CCIfType<[f32], CCAssignToReg<[F0, F1, F2, F3]>>,
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CCIfType<[f64], CCAssignToReg<[D0, D1]>>
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]>;
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// Sparc 32-bit C Calling convention.
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def CC_Sparc32 : CallingConv<[
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//Custom assign SRet to [sp+64].
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@ -34,3 +42,15 @@ def CC_Sparc32 : CallingConv<[
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// Alternatively, they are assigned to the stack in 4-byte aligned units.
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CCAssignToStack<4, 4>
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]>;
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// Sparc 64-bit C Calling convention.
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def CC_Sparc64 : CallingConv<[
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// All integers are promoted to i64 by the caller.
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CCIfType<[i32], CCPromoteToType<i64>>,
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// Integer arguments get passed in integer registers if there is space.
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CCIfType<[i64], CCAssignToReg<[I0, I1, I2, I3, I4, I5]>>,
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// FIXME: Floating point arguments.
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// Alternatively, they are assigned to the stack in 8-byte aligned units.
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CCAssignToStack<8, 8>
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]>;
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@ -93,7 +93,8 @@ SparcTargetLowering::LowerReturn(SDValue Chain,
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DAG.getTarget(), RVLocs, *DAG.getContext());
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// Analize return values.
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CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32);
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CCInfo.AnalyzeReturn(Outs, Subtarget->is64Bit() ?
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RetCC_Sparc64 : RetCC_Sparc32);
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SDValue Flag;
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SmallVector<SDValue, 4> RetOps(1, Chain);
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@ -138,18 +139,32 @@ SparcTargetLowering::LowerReturn(SDValue Chain,
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&RetOps[0], RetOps.size());
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}
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/// LowerFormalArguments - V8 uses a very simple ABI, where all values are
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SDValue SparcTargetLowering::
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LowerFormalArguments(SDValue Chain,
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CallingConv::ID CallConv,
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bool IsVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc DL,
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SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const {
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if (Subtarget->is64Bit())
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return LowerFormalArguments_64(Chain, CallConv, IsVarArg, Ins,
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DL, DAG, InVals);
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return LowerFormalArguments_32(Chain, CallConv, IsVarArg, Ins,
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DL, DAG, InVals);
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}
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/// LowerFormalArguments32 - V8 uses a very simple ABI, where all values are
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/// passed in either one or two GPRs, including FP values. TODO: we should
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/// pass FP values in FP registers for fastcc functions.
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SDValue
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SparcTargetLowering::LowerFormalArguments(SDValue Chain,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg>
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&Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals)
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const {
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SDValue SparcTargetLowering::
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LowerFormalArguments_32(SDValue Chain,
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CallingConv::ID CallConv,
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bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl,
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SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const {
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MachineFunction &MF = DAG.getMachineFunction();
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MachineRegisterInfo &RegInfo = MF.getRegInfo();
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SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
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@ -341,6 +356,63 @@ SparcTargetLowering::LowerFormalArguments(SDValue Chain,
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return Chain;
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}
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// Lower formal arguments for the 64 bit ABI.
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SDValue SparcTargetLowering::
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LowerFormalArguments_64(SDValue Chain,
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CallingConv::ID CallConv,
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bool IsVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc DL,
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SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const {
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MachineFunction &MF = DAG.getMachineFunction();
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// Analyze arguments according to CC_Sparc64.
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
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getTargetMachine(), ArgLocs, *DAG.getContext());
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CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc64);
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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CCValAssign &VA = ArgLocs[i];
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if (VA.isRegLoc()) {
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// This argument is passed in a register.
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// All integer register arguments are promoted by the caller to i64.
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// Create a virtual register for the promoted live-in value.
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unsigned VReg = MF.addLiveIn(VA.getLocReg(),
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getRegClassFor(VA.getLocVT()));
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SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT());
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// The caller promoted the argument, so insert an Assert?ext SDNode so we
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// won't promote the value again in this function.
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switch (VA.getLocInfo()) {
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case CCValAssign::SExt:
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Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg,
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DAG.getValueType(VA.getValVT()));
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break;
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case CCValAssign::ZExt:
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Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg,
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DAG.getValueType(VA.getValVT()));
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break;
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default:
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break;
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}
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// Truncate the register down to the argument type.
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if (VA.isExtInLoc())
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Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
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InVals.push_back(Arg);
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continue;
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}
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// The registers are exhausted. This argument was passed on the stack.
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assert(VA.isMemLoc());
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}
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return Chain;
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}
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SDValue
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SparcTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const {
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@ -77,6 +77,18 @@ namespace llvm {
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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SDValue LowerFormalArguments_32(SDValue Chain,
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CallingConv::ID CallConv,
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bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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SDValue LowerFormalArguments_64(SDValue Chain,
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CallingConv::ID CallConv,
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bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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virtual SDValue
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LowerCall(TargetLowering::CallLoweringInfo &CLI,
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7
test/CodeGen/SPARC/64bit.ll
Normal file
7
test/CodeGen/SPARC/64bit.ll
Normal file
@ -0,0 +1,7 @@
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; RUN: llc < %s -march=sparcv9 | FileCheck %s
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; CHECK: ret2:
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; CHECK: or %g0, %i1, %i0
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define i64 @ret2(i64 %a, i64 %b) {
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ret i64 %b
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}
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@ -1,5 +1,5 @@
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; RUN: llc < %s -march=sparc -mattr=-v9 | not grep popc
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; RUN: llc < %s -march=sparcv9 -mattr=v9 | grep popc
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; RUN: llc < %s -march=sparc -mattr=+v9 | grep popc
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declare i32 @llvm.ctpop.i32(i32)
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