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https://github.com/c64scene-ar/llvm-6502.git
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Add empty patterns for F3_2 instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24771 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
a01b75758c
commit
f3bf50d2c8
@ -77,12 +77,14 @@ class F3_1<bits<2> opVal, bits<6> op3val, dag ops, string asmstr> : F3 {
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let Inst{4-0} = rs2;
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}
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class F3_2<bits<2> opVal, bits<6> op3val, dag ops, string asmstr> : F3 {
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class F3_2<bits<2> opVal, bits<6> op3val, dag ops,
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string asmstr, list<dag> pattern> : F3 {
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bits<13> simm13;
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dag OperandList = ops;
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let AsmString = asmstr;
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let Pattern = pattern;
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let op = opVal;
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let op3 = op3val;
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@ -55,10 +55,10 @@ let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in {
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let rd = I7.Num, rs1 = G0.Num, simm13 = 8 in
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def RET : F3_2<2, 0b111000,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"ret $b, $c, $dst">;
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"ret $b, $c, $dst", []>;
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let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
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def RETL: F3_2<2, 0b111000, (ops),
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"retl">;
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"retl", []>;
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}
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// CMP is a special case of SUBCC where destination is ignored, by setting it to
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// %g0 (hardwired zero).
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@ -66,27 +66,27 @@ let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in {
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let rd = 0 in
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def CMPri: F3_2<2, 0b010100,
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(ops IntRegs:$b, i32imm:$c),
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"cmp $b, $c">;
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"cmp $b, $c", []>;
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// Section B.1 - Load Integer Instructions, p. 90
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def LDSB: F3_2<3, 0b001001,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"ldsb [$b+$c], $dst">;
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"ldsb [$b+$c], $dst", []>;
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def LDSH: F3_2<3, 0b001010,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"ldsh [$b+$c], $dst">;
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"ldsh [$b+$c], $dst", []>;
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def LDUB: F3_2<3, 0b000001,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"ldub [$b+$c], $dst">;
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"ldub [$b+$c], $dst", []>;
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def LDUH: F3_2<3, 0b000010,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"lduh [$b+$c], $dst">;
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"lduh [$b+$c], $dst", []>;
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def LD : F3_2<3, 0b000000,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"ld [$b+$c], $dst">;
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"ld [$b+$c], $dst", []>;
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def LDD : F3_2<3, 0b000011,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"ldd [$b+$c], $dst">;
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"ldd [$b+$c], $dst", []>;
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// Section B.2 - Load Floating-point Instructions, p. 92
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def LDFrr : F3_1<3, 0b100000,
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@ -94,33 +94,33 @@ def LDFrr : F3_1<3, 0b100000,
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"ld [$b+$c], $dst">;
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def LDFri : F3_2<3, 0b100000,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"ld [$b+$c], $dst">;
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"ld [$b+$c], $dst", []>;
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def LDDFrr : F3_1<3, 0b100011,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"ldd [$b+$c], $dst">;
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def LDDFri : F3_2<3, 0b100011,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"ldd [$b+$c], $dst">;
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"ldd [$b+$c], $dst", []>;
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def LDFSRrr: F3_1<3, 0b100001,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"ld [$b+$c], $dst">;
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def LDFSRri: F3_2<3, 0b100001,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"ld [$b+$c], $dst">;
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"ld [$b+$c], $dst", []>;
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// Section B.4 - Store Integer Instructions, p. 95
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def STB : F3_2<3, 0b000101,
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(ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
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"stb $src, [$base+$offset]">;
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"stb $src, [$base+$offset]", []>;
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def STH : F3_2<3, 0b000110,
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(ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
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"sth $src, [$base+$offset]">;
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"sth $src, [$base+$offset]", []>;
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def ST : F3_2<3, 0b000100,
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(ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
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"st $src, [$base+$offset]">;
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"st $src, [$base+$offset]", []>;
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def STD : F3_2<3, 0b000111,
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(ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
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"std $src, [$base+$offset]">;
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"std $src, [$base+$offset]", []>;
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// Section B.5 - Store Floating-point Instructions, p. 97
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def STFrr : F3_1<3, 0b100100,
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@ -128,25 +128,25 @@ def STFrr : F3_1<3, 0b100100,
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"st $src, [$base+$offset]">;
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def STFri : F3_2<3, 0b100100,
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(ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
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"st $src, [$base+$offset]">;
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"st $src, [$base+$offset]", []>;
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def STDFrr : F3_1<3, 0b100111,
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(ops IntRegs:$base, IntRegs:$offset, IntRegs:$src),
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"std $src, [$base+$offset]">;
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def STDFri : F3_2<3, 0b100111,
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(ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
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"std $src, [$base+$offset]">;
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"std $src, [$base+$offset]", []>;
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def STFSRrr : F3_1<3, 0b100101,
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(ops IntRegs:$base, IntRegs:$offset, IntRegs:$src),
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"st $src, [$base+$offset]">;
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def STFSRri : F3_2<3, 0b100101,
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(ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
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"st $src, [$base+$offset]">;
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"st $src, [$base+$offset]", []>;
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def STDFQrr : F3_1<3, 0b100110,
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(ops IntRegs:$base, IntRegs:$offset, IntRegs:$src),
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"std $src, [$base+$offset]">;
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def STDFQri : F3_2<3, 0b100110,
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(ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
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"std $src, [$base+$offset]">;
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"std $src, [$base+$offset]", []>;
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// Section B.9 - SETHI Instruction, p. 104
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def SETHIi: F2_1<0b100,
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@ -164,73 +164,73 @@ def ANDrr : F3_1<2, 0b000001,
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"and $b, $c, $dst">;
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def ANDri : F3_2<2, 0b000001,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"and $b, $c, $dst">;
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"and $b, $c, $dst", []>;
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def ANDCCrr : F3_1<2, 0b010001,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"andcc $b, $c, $dst">;
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def ANDCCri : F3_2<2, 0b010001,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"andcc $b, $c, $dst">;
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"andcc $b, $c, $dst", []>;
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def ANDNrr : F3_1<2, 0b000101,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"andn $b, $c, $dst">;
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def ANDNri : F3_2<2, 0b000101,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"andn $b, $c, $dst">;
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"andn $b, $c, $dst", []>;
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def ANDNCCrr: F3_1<2, 0b010101,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"andncc $b, $c, $dst">;
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def ANDNCCri: F3_2<2, 0b010101,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"andncc $b, $c, $dst">;
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"andncc $b, $c, $dst", []>;
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def ORrr : F3_1<2, 0b000010,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"or $b, $c, $dst">;
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def ORri : F3_2<2, 0b000010,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"or $b, $c, $dst">;
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"or $b, $c, $dst", []>;
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def ORCCrr : F3_1<2, 0b010010,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"orcc $b, $c, $dst">;
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def ORCCri : F3_2<2, 0b010010,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"orcc $b, $c, $dst">;
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"orcc $b, $c, $dst", []>;
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def ORNrr : F3_1<2, 0b000110,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"orn $b, $c, $dst">;
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def ORNri : F3_2<2, 0b000110,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"orn $b, $c, $dst">;
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"orn $b, $c, $dst", []>;
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def ORNCCrr : F3_1<2, 0b010110,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"orncc $b, $c, $dst">;
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def ORNCCri : F3_2<2, 0b010110,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"orncc $b, $c, $dst">;
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"orncc $b, $c, $dst", []>;
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def XORrr : F3_1<2, 0b000011,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"xor $b, $c, $dst">;
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def XORri : F3_2<2, 0b000011,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"xor $b, $c, $dst">;
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"xor $b, $c, $dst", []>;
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def XORCCrr : F3_1<2, 0b010011,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"xorcc $b, $c, $dst">;
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def XORCCri : F3_2<2, 0b010011,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"xorcc $b, $c, $dst">;
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"xorcc $b, $c, $dst", []>;
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def XNORrr : F3_1<2, 0b000111,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"xnor $b, $c, $dst">;
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def XNORri : F3_2<2, 0b000111,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"xnor $b, $c, $dst">;
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"xnor $b, $c, $dst", []>;
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def XNORCCrr: F3_1<2, 0b010111,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"xnorcc $b, $c, $dst">;
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def XNORCCri: F3_2<2, 0b010111,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"xnorcc $b, $c, $dst">;
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"xnorcc $b, $c, $dst", []>;
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// Section B.12 - Shift Instructions, p. 107
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def SLLrr : F3_1<2, 0b100101,
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@ -238,19 +238,19 @@ def SLLrr : F3_1<2, 0b100101,
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"sll $b, $c, $dst">;
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def SLLri : F3_2<2, 0b100101,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"sll $b, $c, $dst">;
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"sll $b, $c, $dst", []>;
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def SRLrr : F3_1<2, 0b100110,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"srl $b, $c, $dst">;
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def SRLri : F3_2<2, 0b100110,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"srl $b, $c, $dst">;
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"srl $b, $c, $dst", []>;
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def SRArr : F3_1<2, 0b100111,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"sra $b, $c, $dst">;
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def SRAri : F3_2<2, 0b100111,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"sla $b, $c, $dst">;
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"sla $b, $c, $dst", []>;
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// Section B.13 - Add Instructions, p. 108
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def ADDrr : F3_1<2, 0b000000,
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@ -258,25 +258,25 @@ def ADDrr : F3_1<2, 0b000000,
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"add $b, $c, $dst">;
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def ADDri : F3_2<2, 0b000000,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"add $b, $c, $dst">;
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"add $b, $c, $dst", []>;
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def ADDCCrr : F3_1<2, 0b010000,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"addcc $b, $c, $dst">;
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def ADDCCri : F3_2<2, 0b010000,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"addcc $b, $c, $dst">;
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"addcc $b, $c, $dst", []>;
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def ADDXrr : F3_1<2, 0b001000,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"addx $b, $c, $dst">;
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def ADDXri : F3_2<2, 0b001000,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"addx $b, $c, $dst">;
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"addx $b, $c, $dst", []>;
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def ADDXCCrr: F3_1<2, 0b011000,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"addxcc $b, $c, $dst">;
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def ADDXCCri: F3_2<2, 0b011000,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"addxcc $b, $c, $dst">;
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"addxcc $b, $c, $dst", []>;
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// Section B.15 - Subtract Instructions, p. 110
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def SUBrr : F3_1<2, 0b000100,
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@ -284,25 +284,25 @@ def SUBrr : F3_1<2, 0b000100,
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"sub $b, $c, $dst">;
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def SUBri : F3_2<2, 0b000100,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"sub $b, $c, $dst">;
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"sub $b, $c, $dst", []>;
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def SUBCCrr : F3_1<2, 0b010100,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"subcc $b, $c, $dst">;
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def SUBCCri : F3_2<2, 0b010100,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"subcc $b, $c, $dst">;
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"subcc $b, $c, $dst", []>;
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def SUBXrr : F3_1<2, 0b001100,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"subx $b, $c, $dst">;
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def SUBXri : F3_2<2, 0b001100,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"subx $b, $c, $dst">;
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"subx $b, $c, $dst", []>;
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def SUBXCCrr: F3_1<2, 0b011100,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"subxcc $b, $c, $dst">;
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def SUBXCCri: F3_2<2, 0b011100,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"subxcc $b, $c, $dst">;
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"subxcc $b, $c, $dst", []>;
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// Section B.18 - Multiply Instructions, p. 113
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def UMULrr : F3_1<2, 0b001010,
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@ -310,25 +310,25 @@ def UMULrr : F3_1<2, 0b001010,
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"umul $b, $c, $dst">;
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def UMULri : F3_2<2, 0b001010,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"umul $b, $c, $dst">;
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"umul $b, $c, $dst", []>;
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def SMULrr : F3_1<2, 0b001011,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"smul $b, $c, $dst">;
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def SMULri : F3_2<2, 0b001011,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"smul $b, $c, $dst">;
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"smul $b, $c, $dst", []>;
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def UMULCCrr: F3_1<2, 0b011010,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"umulcc $b, $c, $dst">;
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def UMULCCri: F3_2<2, 0b011010,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"umulcc $b, $c, $dst">;
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"umulcc $b, $c, $dst", []>;
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def SMULCCrr: F3_1<2, 0b011011,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"smulcc $b, $c, $dst">;
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def SMULCCri: F3_2<2, 0b011011,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"smulcc $b, $c, $dst">;
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||||
"smulcc $b, $c, $dst", []>;
|
||||
|
||||
// Section B.19 - Divide Instructions, p. 115
|
||||
def UDIVrr : F3_1<2, 0b001110,
|
||||
@ -336,25 +336,25 @@ def UDIVrr : F3_1<2, 0b001110,
|
||||
"udiv $b, $c, $dst">;
|
||||
def UDIVri : F3_2<2, 0b001110,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"udiv $b, $c, $dst">;
|
||||
"udiv $b, $c, $dst", []>;
|
||||
def SDIVrr : F3_1<2, 0b001111,
|
||||
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
|
||||
"sdiv $b, $c, $dst">;
|
||||
def SDIVri : F3_2<2, 0b001111,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"sdiv $b, $c, $dst">;
|
||||
"sdiv $b, $c, $dst", []>;
|
||||
def UDIVCCrr : F3_1<2, 0b011110,
|
||||
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
|
||||
"udivcc $b, $c, $dst">;
|
||||
def UDIVCCri : F3_2<2, 0b011110,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"udivcc $b, $c, $dst">;
|
||||
"udivcc $b, $c, $dst", []>;
|
||||
def SDIVCCrr : F3_1<2, 0b011111,
|
||||
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
|
||||
"sdivcc $b, $c, $dst">;
|
||||
def SDIVCCri : F3_2<2, 0b011111,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"sdivcc $b, $c, $dst">;
|
||||
"sdivcc $b, $c, $dst", []>;
|
||||
|
||||
// Section B.20 - SAVE and RESTORE, p. 117
|
||||
def SAVErr : F3_1<2, 0b111100,
|
||||
@ -362,13 +362,13 @@ def SAVErr : F3_1<2, 0b111100,
|
||||
"save $b, $c, $dst">;
|
||||
def SAVEri : F3_2<2, 0b111100,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"save $b, $c, $dst">;
|
||||
"save $b, $c, $dst", []>;
|
||||
def RESTORErr : F3_1<2, 0b111101,
|
||||
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
|
||||
"restore $b, $c, $dst">;
|
||||
def RESTOREri : F3_2<2, 0b111101,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"restore $b, $c, $dst">;
|
||||
"restore $b, $c, $dst", []>;
|
||||
|
||||
// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
|
||||
|
||||
@ -452,7 +452,7 @@ def WRrr : F3_1<2, 0b110000,
|
||||
"wr $b, $c, $dst">;
|
||||
def WRri : F3_2<2, 0b110000,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"wr $b, $c, $dst">;
|
||||
"wr $b, $c, $dst", []>;
|
||||
|
||||
// Convert Integer to Floating-point Instructions, p. 141
|
||||
def FITOS : F3_3<2, 0b110100, 0b011000100,
|
||||
|
||||
@ -77,12 +77,14 @@ class F3_1<bits<2> opVal, bits<6> op3val, dag ops, string asmstr> : F3 {
|
||||
let Inst{4-0} = rs2;
|
||||
}
|
||||
|
||||
class F3_2<bits<2> opVal, bits<6> op3val, dag ops, string asmstr> : F3 {
|
||||
class F3_2<bits<2> opVal, bits<6> op3val, dag ops,
|
||||
string asmstr, list<dag> pattern> : F3 {
|
||||
bits<13> simm13;
|
||||
|
||||
dag OperandList = ops;
|
||||
let AsmString = asmstr;
|
||||
|
||||
let Pattern = pattern;
|
||||
|
||||
let op = opVal;
|
||||
let op3 = op3val;
|
||||
|
||||
|
||||
@ -55,10 +55,10 @@ let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in {
|
||||
let rd = I7.Num, rs1 = G0.Num, simm13 = 8 in
|
||||
def RET : F3_2<2, 0b111000,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"ret $b, $c, $dst">;
|
||||
"ret $b, $c, $dst", []>;
|
||||
let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
|
||||
def RETL: F3_2<2, 0b111000, (ops),
|
||||
"retl">;
|
||||
"retl", []>;
|
||||
}
|
||||
// CMP is a special case of SUBCC where destination is ignored, by setting it to
|
||||
// %g0 (hardwired zero).
|
||||
@ -66,27 +66,27 @@ let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in {
|
||||
let rd = 0 in
|
||||
def CMPri: F3_2<2, 0b010100,
|
||||
(ops IntRegs:$b, i32imm:$c),
|
||||
"cmp $b, $c">;
|
||||
"cmp $b, $c", []>;
|
||||
|
||||
// Section B.1 - Load Integer Instructions, p. 90
|
||||
def LDSB: F3_2<3, 0b001001,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"ldsb [$b+$c], $dst">;
|
||||
"ldsb [$b+$c], $dst", []>;
|
||||
def LDSH: F3_2<3, 0b001010,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"ldsh [$b+$c], $dst">;
|
||||
"ldsh [$b+$c], $dst", []>;
|
||||
def LDUB: F3_2<3, 0b000001,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"ldub [$b+$c], $dst">;
|
||||
"ldub [$b+$c], $dst", []>;
|
||||
def LDUH: F3_2<3, 0b000010,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"lduh [$b+$c], $dst">;
|
||||
"lduh [$b+$c], $dst", []>;
|
||||
def LD : F3_2<3, 0b000000,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"ld [$b+$c], $dst">;
|
||||
"ld [$b+$c], $dst", []>;
|
||||
def LDD : F3_2<3, 0b000011,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"ldd [$b+$c], $dst">;
|
||||
"ldd [$b+$c], $dst", []>;
|
||||
|
||||
// Section B.2 - Load Floating-point Instructions, p. 92
|
||||
def LDFrr : F3_1<3, 0b100000,
|
||||
@ -94,33 +94,33 @@ def LDFrr : F3_1<3, 0b100000,
|
||||
"ld [$b+$c], $dst">;
|
||||
def LDFri : F3_2<3, 0b100000,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"ld [$b+$c], $dst">;
|
||||
"ld [$b+$c], $dst", []>;
|
||||
def LDDFrr : F3_1<3, 0b100011,
|
||||
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
|
||||
"ldd [$b+$c], $dst">;
|
||||
def LDDFri : F3_2<3, 0b100011,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"ldd [$b+$c], $dst">;
|
||||
"ldd [$b+$c], $dst", []>;
|
||||
def LDFSRrr: F3_1<3, 0b100001,
|
||||
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
|
||||
"ld [$b+$c], $dst">;
|
||||
def LDFSRri: F3_2<3, 0b100001,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"ld [$b+$c], $dst">;
|
||||
"ld [$b+$c], $dst", []>;
|
||||
|
||||
// Section B.4 - Store Integer Instructions, p. 95
|
||||
def STB : F3_2<3, 0b000101,
|
||||
(ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
|
||||
"stb $src, [$base+$offset]">;
|
||||
"stb $src, [$base+$offset]", []>;
|
||||
def STH : F3_2<3, 0b000110,
|
||||
(ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
|
||||
"sth $src, [$base+$offset]">;
|
||||
"sth $src, [$base+$offset]", []>;
|
||||
def ST : F3_2<3, 0b000100,
|
||||
(ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
|
||||
"st $src, [$base+$offset]">;
|
||||
"st $src, [$base+$offset]", []>;
|
||||
def STD : F3_2<3, 0b000111,
|
||||
(ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
|
||||
"std $src, [$base+$offset]">;
|
||||
"std $src, [$base+$offset]", []>;
|
||||
|
||||
// Section B.5 - Store Floating-point Instructions, p. 97
|
||||
def STFrr : F3_1<3, 0b100100,
|
||||
@ -128,25 +128,25 @@ def STFrr : F3_1<3, 0b100100,
|
||||
"st $src, [$base+$offset]">;
|
||||
def STFri : F3_2<3, 0b100100,
|
||||
(ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
|
||||
"st $src, [$base+$offset]">;
|
||||
"st $src, [$base+$offset]", []>;
|
||||
def STDFrr : F3_1<3, 0b100111,
|
||||
(ops IntRegs:$base, IntRegs:$offset, IntRegs:$src),
|
||||
"std $src, [$base+$offset]">;
|
||||
def STDFri : F3_2<3, 0b100111,
|
||||
(ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
|
||||
"std $src, [$base+$offset]">;
|
||||
"std $src, [$base+$offset]", []>;
|
||||
def STFSRrr : F3_1<3, 0b100101,
|
||||
(ops IntRegs:$base, IntRegs:$offset, IntRegs:$src),
|
||||
"st $src, [$base+$offset]">;
|
||||
def STFSRri : F3_2<3, 0b100101,
|
||||
(ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
|
||||
"st $src, [$base+$offset]">;
|
||||
"st $src, [$base+$offset]", []>;
|
||||
def STDFQrr : F3_1<3, 0b100110,
|
||||
(ops IntRegs:$base, IntRegs:$offset, IntRegs:$src),
|
||||
"std $src, [$base+$offset]">;
|
||||
def STDFQri : F3_2<3, 0b100110,
|
||||
(ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
|
||||
"std $src, [$base+$offset]">;
|
||||
"std $src, [$base+$offset]", []>;
|
||||
|
||||
// Section B.9 - SETHI Instruction, p. 104
|
||||
def SETHIi: F2_1<0b100,
|
||||
@ -164,73 +164,73 @@ def ANDrr : F3_1<2, 0b000001,
|
||||
"and $b, $c, $dst">;
|
||||
def ANDri : F3_2<2, 0b000001,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"and $b, $c, $dst">;
|
||||
"and $b, $c, $dst", []>;
|
||||
def ANDCCrr : F3_1<2, 0b010001,
|
||||
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
|
||||
"andcc $b, $c, $dst">;
|
||||
def ANDCCri : F3_2<2, 0b010001,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"andcc $b, $c, $dst">;
|
||||
"andcc $b, $c, $dst", []>;
|
||||
def ANDNrr : F3_1<2, 0b000101,
|
||||
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
|
||||
"andn $b, $c, $dst">;
|
||||
def ANDNri : F3_2<2, 0b000101,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"andn $b, $c, $dst">;
|
||||
"andn $b, $c, $dst", []>;
|
||||
def ANDNCCrr: F3_1<2, 0b010101,
|
||||
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
|
||||
"andncc $b, $c, $dst">;
|
||||
def ANDNCCri: F3_2<2, 0b010101,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"andncc $b, $c, $dst">;
|
||||
"andncc $b, $c, $dst", []>;
|
||||
def ORrr : F3_1<2, 0b000010,
|
||||
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
|
||||
"or $b, $c, $dst">;
|
||||
def ORri : F3_2<2, 0b000010,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"or $b, $c, $dst">;
|
||||
"or $b, $c, $dst", []>;
|
||||
def ORCCrr : F3_1<2, 0b010010,
|
||||
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
|
||||
"orcc $b, $c, $dst">;
|
||||
def ORCCri : F3_2<2, 0b010010,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"orcc $b, $c, $dst">;
|
||||
"orcc $b, $c, $dst", []>;
|
||||
def ORNrr : F3_1<2, 0b000110,
|
||||
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
|
||||
"orn $b, $c, $dst">;
|
||||
def ORNri : F3_2<2, 0b000110,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"orn $b, $c, $dst">;
|
||||
"orn $b, $c, $dst", []>;
|
||||
def ORNCCrr : F3_1<2, 0b010110,
|
||||
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
|
||||
"orncc $b, $c, $dst">;
|
||||
def ORNCCri : F3_2<2, 0b010110,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"orncc $b, $c, $dst">;
|
||||
"orncc $b, $c, $dst", []>;
|
||||
def XORrr : F3_1<2, 0b000011,
|
||||
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
|
||||
"xor $b, $c, $dst">;
|
||||
def XORri : F3_2<2, 0b000011,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"xor $b, $c, $dst">;
|
||||
"xor $b, $c, $dst", []>;
|
||||
def XORCCrr : F3_1<2, 0b010011,
|
||||
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
|
||||
"xorcc $b, $c, $dst">;
|
||||
def XORCCri : F3_2<2, 0b010011,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"xorcc $b, $c, $dst">;
|
||||
"xorcc $b, $c, $dst", []>;
|
||||
def XNORrr : F3_1<2, 0b000111,
|
||||
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
|
||||
"xnor $b, $c, $dst">;
|
||||
def XNORri : F3_2<2, 0b000111,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"xnor $b, $c, $dst">;
|
||||
"xnor $b, $c, $dst", []>;
|
||||
def XNORCCrr: F3_1<2, 0b010111,
|
||||
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
|
||||
"xnorcc $b, $c, $dst">;
|
||||
def XNORCCri: F3_2<2, 0b010111,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"xnorcc $b, $c, $dst">;
|
||||
"xnorcc $b, $c, $dst", []>;
|
||||
|
||||
// Section B.12 - Shift Instructions, p. 107
|
||||
def SLLrr : F3_1<2, 0b100101,
|
||||
@ -238,19 +238,19 @@ def SLLrr : F3_1<2, 0b100101,
|
||||
"sll $b, $c, $dst">;
|
||||
def SLLri : F3_2<2, 0b100101,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"sll $b, $c, $dst">;
|
||||
"sll $b, $c, $dst", []>;
|
||||
def SRLrr : F3_1<2, 0b100110,
|
||||
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
|
||||
"srl $b, $c, $dst">;
|
||||
def SRLri : F3_2<2, 0b100110,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"srl $b, $c, $dst">;
|
||||
"srl $b, $c, $dst", []>;
|
||||
def SRArr : F3_1<2, 0b100111,
|
||||
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
|
||||
"sra $b, $c, $dst">;
|
||||
def SRAri : F3_2<2, 0b100111,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"sla $b, $c, $dst">;
|
||||
"sla $b, $c, $dst", []>;
|
||||
|
||||
// Section B.13 - Add Instructions, p. 108
|
||||
def ADDrr : F3_1<2, 0b000000,
|
||||
@ -258,25 +258,25 @@ def ADDrr : F3_1<2, 0b000000,
|
||||
"add $b, $c, $dst">;
|
||||
def ADDri : F3_2<2, 0b000000,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"add $b, $c, $dst">;
|
||||
"add $b, $c, $dst", []>;
|
||||
def ADDCCrr : F3_1<2, 0b010000,
|
||||
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
|
||||
"addcc $b, $c, $dst">;
|
||||
def ADDCCri : F3_2<2, 0b010000,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"addcc $b, $c, $dst">;
|
||||
"addcc $b, $c, $dst", []>;
|
||||
def ADDXrr : F3_1<2, 0b001000,
|
||||
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
|
||||
"addx $b, $c, $dst">;
|
||||
def ADDXri : F3_2<2, 0b001000,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"addx $b, $c, $dst">;
|
||||
"addx $b, $c, $dst", []>;
|
||||
def ADDXCCrr: F3_1<2, 0b011000,
|
||||
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
|
||||
"addxcc $b, $c, $dst">;
|
||||
def ADDXCCri: F3_2<2, 0b011000,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"addxcc $b, $c, $dst">;
|
||||
"addxcc $b, $c, $dst", []>;
|
||||
|
||||
// Section B.15 - Subtract Instructions, p. 110
|
||||
def SUBrr : F3_1<2, 0b000100,
|
||||
@ -284,25 +284,25 @@ def SUBrr : F3_1<2, 0b000100,
|
||||
"sub $b, $c, $dst">;
|
||||
def SUBri : F3_2<2, 0b000100,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"sub $b, $c, $dst">;
|
||||
"sub $b, $c, $dst", []>;
|
||||
def SUBCCrr : F3_1<2, 0b010100,
|
||||
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
|
||||
"subcc $b, $c, $dst">;
|
||||
def SUBCCri : F3_2<2, 0b010100,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"subcc $b, $c, $dst">;
|
||||
"subcc $b, $c, $dst", []>;
|
||||
def SUBXrr : F3_1<2, 0b001100,
|
||||
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
|
||||
"subx $b, $c, $dst">;
|
||||
def SUBXri : F3_2<2, 0b001100,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"subx $b, $c, $dst">;
|
||||
"subx $b, $c, $dst", []>;
|
||||
def SUBXCCrr: F3_1<2, 0b011100,
|
||||
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
|
||||
"subxcc $b, $c, $dst">;
|
||||
def SUBXCCri: F3_2<2, 0b011100,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"subxcc $b, $c, $dst">;
|
||||
"subxcc $b, $c, $dst", []>;
|
||||
|
||||
// Section B.18 - Multiply Instructions, p. 113
|
||||
def UMULrr : F3_1<2, 0b001010,
|
||||
@ -310,25 +310,25 @@ def UMULrr : F3_1<2, 0b001010,
|
||||
"umul $b, $c, $dst">;
|
||||
def UMULri : F3_2<2, 0b001010,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"umul $b, $c, $dst">;
|
||||
"umul $b, $c, $dst", []>;
|
||||
def SMULrr : F3_1<2, 0b001011,
|
||||
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
|
||||
"smul $b, $c, $dst">;
|
||||
def SMULri : F3_2<2, 0b001011,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"smul $b, $c, $dst">;
|
||||
"smul $b, $c, $dst", []>;
|
||||
def UMULCCrr: F3_1<2, 0b011010,
|
||||
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
|
||||
"umulcc $b, $c, $dst">;
|
||||
def UMULCCri: F3_2<2, 0b011010,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"umulcc $b, $c, $dst">;
|
||||
"umulcc $b, $c, $dst", []>;
|
||||
def SMULCCrr: F3_1<2, 0b011011,
|
||||
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
|
||||
"smulcc $b, $c, $dst">;
|
||||
def SMULCCri: F3_2<2, 0b011011,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"smulcc $b, $c, $dst">;
|
||||
"smulcc $b, $c, $dst", []>;
|
||||
|
||||
// Section B.19 - Divide Instructions, p. 115
|
||||
def UDIVrr : F3_1<2, 0b001110,
|
||||
@ -336,25 +336,25 @@ def UDIVrr : F3_1<2, 0b001110,
|
||||
"udiv $b, $c, $dst">;
|
||||
def UDIVri : F3_2<2, 0b001110,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"udiv $b, $c, $dst">;
|
||||
"udiv $b, $c, $dst", []>;
|
||||
def SDIVrr : F3_1<2, 0b001111,
|
||||
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
|
||||
"sdiv $b, $c, $dst">;
|
||||
def SDIVri : F3_2<2, 0b001111,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"sdiv $b, $c, $dst">;
|
||||
"sdiv $b, $c, $dst", []>;
|
||||
def UDIVCCrr : F3_1<2, 0b011110,
|
||||
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
|
||||
"udivcc $b, $c, $dst">;
|
||||
def UDIVCCri : F3_2<2, 0b011110,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"udivcc $b, $c, $dst">;
|
||||
"udivcc $b, $c, $dst", []>;
|
||||
def SDIVCCrr : F3_1<2, 0b011111,
|
||||
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
|
||||
"sdivcc $b, $c, $dst">;
|
||||
def SDIVCCri : F3_2<2, 0b011111,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"sdivcc $b, $c, $dst">;
|
||||
"sdivcc $b, $c, $dst", []>;
|
||||
|
||||
// Section B.20 - SAVE and RESTORE, p. 117
|
||||
def SAVErr : F3_1<2, 0b111100,
|
||||
@ -362,13 +362,13 @@ def SAVErr : F3_1<2, 0b111100,
|
||||
"save $b, $c, $dst">;
|
||||
def SAVEri : F3_2<2, 0b111100,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"save $b, $c, $dst">;
|
||||
"save $b, $c, $dst", []>;
|
||||
def RESTORErr : F3_1<2, 0b111101,
|
||||
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
|
||||
"restore $b, $c, $dst">;
|
||||
def RESTOREri : F3_2<2, 0b111101,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"restore $b, $c, $dst">;
|
||||
"restore $b, $c, $dst", []>;
|
||||
|
||||
// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
|
||||
|
||||
@ -452,7 +452,7 @@ def WRrr : F3_1<2, 0b110000,
|
||||
"wr $b, $c, $dst">;
|
||||
def WRri : F3_2<2, 0b110000,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"wr $b, $c, $dst">;
|
||||
"wr $b, $c, $dst", []>;
|
||||
|
||||
// Convert Integer to Floating-point Instructions, p. 141
|
||||
def FITOS : F3_3<2, 0b110100, 0b011000100,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user