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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-17 21:29:20 +00:00
Added lazy function resolution to the JIT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6633 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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@ -54,10 +54,13 @@ namespace {
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return SparcV9.getBinaryCodeForInstr(MI);
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}
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inline uint64_t insertFarJumpAtAddr(int64_t Value, uint64_t Addr);
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private:
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uint64_t emitStubForFunction(Function *F);
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static void CompilationCallback();
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uint64_t resolveFunctionReference(uint64_t RetAddr);
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};
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JITResolver *TheJITResolver;
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@ -92,27 +95,175 @@ uint64_t JITResolver::getLazyResolver(Function *F) {
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return Stub;
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}
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uint64_t JITResolver::insertFarJumpAtAddr(int64_t Target, uint64_t Addr) {
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static const unsigned i1 = SparcIntRegClass::i1, i2 = SparcIntRegClass::i2,
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i7 = SparcIntRegClass::i7,
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o6 = SparcIntRegClass::o6, g0 = SparcIntRegClass::g0;
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//
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// Save %i1, %i2 to the stack so we can form a 64-bit constant in %i2
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//
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// stx %i1, [%sp + 2119] ;; save %i1 to the stack, used as temp
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MachineInstr *STX = BuildMI(V9::STXi, 3).addReg(i1).addReg(o6).addSImm(2119);
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*((unsigned*)(intptr_t)Addr) = getBinaryCodeForInstr(*STX);
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delete STX;
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Addr += 4;
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// stx %i2, [%sp + 2127] ;; save %i2 to the stack
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STX = BuildMI(V9::STXi, 3).addReg(i2).addReg(o6).addSImm(2127);
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*((unsigned*)(intptr_t)Addr) = getBinaryCodeForInstr(*STX);
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delete STX;
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Addr += 4;
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//
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// Get address to branch into %i2, using %i1 as a temporary
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//
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// sethi %uhi(Target), %i1 ;; get upper 22 bits of Target into %i1
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MachineInstr *SH = BuildMI(V9::SETHI, 2).addSImm(Target >> 42).addReg(i1);
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*((unsigned*)(intptr_t)Addr) = getBinaryCodeForInstr(*SH);
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delete SH;
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Addr += 4;
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// or %i1, %ulo(Target), %i1 ;; get 10 lower bits of upper word into %1
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MachineInstr *OR = BuildMI(V9::ORi, 3)
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.addReg(i1).addSImm((Target >> 32) & 0x03ff).addReg(i1);
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*((unsigned*)(intptr_t)Addr) = getBinaryCodeForInstr(*OR);
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delete OR;
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Addr += 4;
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// sllx %i1, 32, %i1 ;; shift those 10 bits to the upper word
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MachineInstr *SL = BuildMI(V9::SLLXi6, 3).addReg(i1).addSImm(32).addReg(i1);
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*((unsigned*)(intptr_t)Addr) = getBinaryCodeForInstr(*SL);
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delete SL;
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Addr += 4;
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// sethi %hi(Target), %i2 ;; extract bits 10-31 into the dest reg
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SH = BuildMI(V9::SETHI, 2).addSImm((Target >> 10) & 0x03fffff).addReg(i2);
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*((unsigned*)(intptr_t)Addr) = getBinaryCodeForInstr(*SH);
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delete SH;
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Addr += 4;
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// or %i1, %i2, %i2 ;; get upper word (in %i1) into %i2
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OR = BuildMI(V9::ORr, 3).addReg(i1).addReg(i2).addReg(i2);
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*((unsigned*)(intptr_t)Addr) = getBinaryCodeForInstr(*OR);
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delete OR;
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Addr += 4;
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// or %i2, %lo(Target), %i2 ;; get lowest 10 bits of Target into %i2
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OR = BuildMI(V9::ORi, 3).addReg(i2).addSImm(Target & 0x03ff).addReg(i2);
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*((unsigned*)(intptr_t)Addr) = getBinaryCodeForInstr(*OR);
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delete OR;
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Addr += 4;
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// ldx [%sp + 2119], %i1 ;; restore %i1 -> 2119 = BIAS(2047) + 72
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MachineInstr *LDX = BuildMI(V9::LDXi, 3).addReg(o6).addSImm(2119).addReg(i1);
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*((unsigned*)(intptr_t)Addr) = getBinaryCodeForInstr(*LDX);
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delete LDX;
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Addr += 4;
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// jmpl %i2, %g0, %g0 ;; indirect branch on %i2
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MachineInstr *J = BuildMI(V9::JMPLRETr, 3).addReg(i2).addReg(g0).addReg(g0);
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*((unsigned*)(intptr_t)Addr) = getBinaryCodeForInstr(*J);
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delete J;
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Addr += 4;
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// ldx [%sp + 2127], %i2 ;; restore %i2 -> 2127 = BIAS(2047) + 80
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LDX = BuildMI(V9::LDXi, 3).addReg(o6).addSImm(2127).addReg(i2);
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*((unsigned*)(intptr_t)Addr) = getBinaryCodeForInstr(*LDX);
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delete LDX;
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Addr += 4;
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return Addr;
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}
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void JITResolver::CompilationCallback() {
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uint64_t *StackPtr = (uint64_t*)__builtin_frame_address(0);
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uint64_t RetAddr = (uint64_t)(intptr_t)__builtin_return_address(0);
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std::cerr << "In callback! Addr=0x" << std::hex << RetAddr
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<< " SP=0x" << (uint64_t)(intptr_t)StackPtr << std::dec << "\n";
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int64_t NewVal = (int64_t)TheJITResolver->resolveFunctionReference(RetAddr);
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uint64_t CameFrom = (uint64_t)(intptr_t)__builtin_return_address(0);
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int64_t Target = (int64_t)TheJITResolver->resolveFunctionReference(CameFrom);
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std::cerr << "In callback! Addr=0x" << std::hex << CameFrom << "\n";
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// Rewrite the call target... so that we don't fault every time we execute
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// the call.
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#if 0
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int64_t RealCallTarget = (int64_t)
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((NewVal - TheJITResolver->getCurrentPCValue()) >> 4);
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MachineInstr *MI = BuildMI(V9::CALL, 1);
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MI->addSignExtImmOperand(RealCallTarget);
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// FIXME: this could be in the wrong byte order!!
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*((unsigned*)(intptr_t)RetAddr) = TheJITResolver->getBinaryCodeForInstr(*MI);
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if (RealCallTarget >= (1<<22) || RealCallTarget <= -(1<<22)) {
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std::cerr << "Address out of bounds for 22bit BA: " << RealCallTarget<<"\n";
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abort();
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}
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#endif
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//uint64_t CurrPC = TheJITResolver->getCurrentPCValue();
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// we will insert 9 instructions before we do the actual jump
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//int64_t NewTarget = (NewVal - 9*4 - InstAddr) >> 2;
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static const unsigned i1 = SparcIntRegClass::i1, i2 = SparcIntRegClass::i2,
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i7 = SparcIntRegClass::i7, o6 = SparcIntRegClass::o6,
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o7 = SparcIntRegClass::o7, g0 = SparcIntRegClass::g0;
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// Subtract 4 to overwrite the 'save' that's there now
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uint64_t InstAddr = CameFrom-4;
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InstAddr = TheJITResolver->insertFarJumpAtAddr(Target, InstAddr);
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// CODE SHOULD NEVER GO PAST THIS LOAD!! The real function should return to
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// the original caller, not here!!
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// FIXME: add call 0 to make sure?!?
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// =============== THE REAL STUB ENDS HERE =========================
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// What follows below is one-time restore code, because this callback may be
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// changing registers in unpredictible ways. However, since it is executed
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// only once per function (after the function is resolved, the callback is no
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// longer in the path), this has to be done only once.
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//
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// Thus, it is after the regular stub code. The call back returns to THIS
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// point, but every other call to the target function will execute the code
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// above. Hence, this code is one-time use.
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uint64_t OneTimeRestore = InstAddr;
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// restore %g0, 0, %g0
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//MachineInstr *R = BuildMI(V9::RESTOREi, 3).addMReg(g0).addSImm(0)
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// .addMReg(g0, MOTy::Def);
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//*((unsigned*)(intptr_t)InstAddr)=TheJITResolver->getBinaryCodeForInstr(*R);
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//delete R;
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// FIXME: BuildMI() above crashes. Encode the instruction directly.
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// restore %g0, 0, %g0
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*((unsigned*)(intptr_t)InstAddr) = 0x81e82000U;
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InstAddr += 4;
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InstAddr = TheJITResolver->insertFarJumpAtAddr(Target, InstAddr);
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// FIXME: if the target function is close enough to fit into the 19bit disp of
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// BA, we should use this version, as its much cheaper to generate.
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/*
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MachineInstr *MI = BuildMI(V9::BA, 1).addSImm(RealCallTarget);
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*((unsigned*)(intptr_t)InstAddr) = TheJITResolver->getBinaryCodeForInstr(*MI);
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delete MI;
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InstAddr += 4;
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// Add another NOP
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MachineInstr *Nop = BuildMI(V9::NOP, 0);
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*((unsigned*)(intptr_t)InstAddr)=TheJITResolver->getBinaryCodeForInstr(*Nop);
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delete Nop;
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InstAddr += 4;
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MachineInstr *BA = BuildMI(V9::BA, 1).addSImm(RealCallTarget-2);
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*((unsigned*)(intptr_t)InstAddr) = TheJITResolver->getBinaryCodeForInstr(*BA);
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delete BA;
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*/
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// Change the return address to reexecute the call instruction...
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StackPtr[1] -= 4;
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// The return address is really %o7, but will disappear after this function
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// returns, and the register windows are rotated away.
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#if defined(sparc) || defined(__sparc__) || defined(__sparcv9)
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__asm__ __volatile__ ("or %%g0, %0, %%i7" : : "r" (OneTimeRestore-8));
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#endif
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}
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/// emitStubForFunction - This method is used by the JIT when it needs to emit
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@ -122,26 +273,31 @@ void JITResolver::CompilationCallback() {
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/// directly.
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///
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uint64_t JITResolver::emitStubForFunction(Function *F) {
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#if 0
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MCE.startFunctionStub(*F, 6);
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MCE.emitByte(0xE8); // Call with 32 bit pc-rel destination...
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uint64_t Address = addFunctionReference(MCE.getCurrentPCValue(), F);
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MCE.emitWord(Address-MCE.getCurrentPCValue()-4);
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std::cerr << "Emitting stub at addr: 0x"
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<< std::hex << MCE.getCurrentPCValue() << "\n";
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MCE.emitByte(0xCD); // Interrupt - Just a marker identifying the stub!
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return (intptr_t)MCE.finishFunctionStub(*F);
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#endif
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MCE.startFunctionStub(*F, 6);
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unsigned o6 = SparcIntRegClass::o6;
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// save %sp, -192, %sp
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MachineInstr *SV = BuildMI(V9::SAVEi, 3).addReg(o6).addSImm(-192).addReg(o6);
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SparcV9.emitWord(SparcV9.getBinaryCodeForInstr(*SV));
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delete SV;
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int64_t CurrPC = MCE.getCurrentPCValue();
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int64_t Addr = (int64_t)addFunctionReference(CurrPC, F);
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int64_t CallTarget = (Addr-CurrPC) >> 2;
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MachineInstr *Call = BuildMI(V9::CALL, 1);
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Call->addSignExtImmOperand(CallTarget);
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if (CallTarget >= (1 << 30) || CallTarget <= -(1 << 30)) {
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std::cerr << "Call target beyond 30 bit limit of CALL: " <<CallTarget<<"\n";
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abort();
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}
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// call CallTarget ;; invoke the callback
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MachineInstr *Call = BuildMI(V9::CALL, 1).addSImm(CallTarget);
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SparcV9.emitWord(SparcV9.getBinaryCodeForInstr(*Call));
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delete Call;
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// nop ;; call delay slot
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MachineInstr *Nop = BuildMI(V9::NOP, 0);
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SparcV9.emitWord(SparcV9.getBinaryCodeForInstr(*Nop));
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delete Nop;
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@ -170,7 +326,25 @@ void SparcV9CodeEmitter::emitWord(unsigned Val) {
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}
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}
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unsigned getRealRegNum(unsigned fakeReg, unsigned regClass) {
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bool SparcV9CodeEmitter::isFPInstr(MachineInstr &MI) {
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for (unsigned i = 0, e = MI.getNumOperands(); i < e; ++i) {
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const MachineOperand &MO = MI.getOperand(i);
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if (MO.isPhysicalRegister()) {
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unsigned fakeReg = MO.getReg(), realReg, regClass, regType;
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regType = TM.getRegInfo().getRegType(fakeReg);
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// At least map fakeReg into its class
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fakeReg = TM.getRegInfo().getClassRegNum(fakeReg, regClass);
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if (regClass == UltraSparcRegInfo::FPSingleRegType ||
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regClass == UltraSparcRegInfo::FPDoubleRegType)
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return true;
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}
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}
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return false;
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}
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unsigned
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SparcV9CodeEmitter::getRealRegNum(unsigned fakeReg, unsigned regClass,
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MachineInstr &MI) {
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switch (regClass) {
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case UltraSparcRegInfo::IntRegType: {
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// Sparc manual, p31
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@ -199,11 +373,23 @@ unsigned getRealRegNum(unsigned fakeReg, unsigned regClass) {
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return fakeReg;
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}
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case UltraSparcRegInfo::FloatCCRegType: {
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/* These are laid out %fcc0 - %fcc3 => 0 - 3, so are correct */
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return fakeReg;
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}
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case UltraSparcRegInfo::IntCCRegType: {
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return fakeReg;
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static const unsigned FPInstrIntCCReg[] = { 6 /* xcc */, 4 /* icc */ };
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static const unsigned IntInstrIntCCReg[] = { 2 /* xcc */, 0 /* icc */ };
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if (isFPInstr(MI)) {
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assert(fakeReg < sizeof(FPInstrIntCCReg)/sizeof(FPInstrIntCCReg[0])
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&& "Int CC register out of bounds for FPInstr IntCCReg map");
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return FPInstrIntCCReg[fakeReg];
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} else {
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assert(fakeReg < sizeof(IntInstrIntCCReg)/sizeof(IntInstrIntCCReg[0])
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&& "Int CC register out of bounds for IntInstr IntCCReg map");
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return IntInstrIntCCReg[fakeReg];
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}
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}
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default:
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assert(0 && "Invalid unified register number in getRegType");
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@ -278,7 +464,9 @@ int64_t SparcV9CodeEmitter::getMachineOpValue(MachineInstr &MI,
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std::cerr << "ERROR: PC relative disp unhandled:" << MO << "\n";
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abort();
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}
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} else if (MO.isPhysicalRegister()) {
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} else if (MO.isPhysicalRegister() ||
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MO.getType() == MachineOperand::MO_CCRegister)
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{
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// This is necessary because the Sparc doesn't actually lay out registers
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// in the real fashion -- it skips those that it chooses not to allocate,
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// i.e. those that are the SP, etc.
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@ -287,7 +475,7 @@ int64_t SparcV9CodeEmitter::getMachineOpValue(MachineInstr &MI,
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// At least map fakeReg into its class
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fakeReg = TM.getRegInfo().getClassRegNum(fakeReg, regClass);
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// Find the real register number for use in an instruction
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realReg = getRealRegNum(fakeReg, regClass);
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realReg = getRealRegNum(fakeReg, regClass, MI);
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std::cerr << "Reg[" << std::dec << fakeReg << "] = " << realReg << "\n";
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rv = realReg;
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} else if (MO.isImmediate()) {
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@ -327,13 +515,13 @@ int64_t SparcV9CodeEmitter::getMachineOpValue(MachineInstr &MI,
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// are used in SPARC assembly. (Some of these make no sense in combination
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// with some of the above; we'll trust that the instruction selector
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// will not produce nonsense, and not check for valid combinations here.)
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if (MO.opLoBits32()) { // %lo(val)
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if (MO.opLoBits32()) { // %lo(val) == %lo() in Sparc ABI doc
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return rv & 0x03ff;
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} else if (MO.opHiBits32()) { // %lm(val)
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} else if (MO.opHiBits32()) { // %lm(val) == %hi() in Sparc ABI doc
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return (rv >> 10) & 0x03fffff;
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} else if (MO.opLoBits64()) { // %hm(val)
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} else if (MO.opLoBits64()) { // %hm(val) == %ulo() in Sparc ABI doc
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return (rv >> 32) & 0x03ff;
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} else if (MO.opHiBits64()) { // %hh(val)
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} else if (MO.opHiBits64()) { // %hh(val) == %uhi() in Sparc ABI doc
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return rv >> 42;
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} else { // (unadorned) val
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return rv;
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@ -47,6 +47,10 @@ private:
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void emitBasicBlock(MachineBasicBlock &MBB);
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void* getGlobalAddress(GlobalValue *V, MachineInstr &MI,
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bool isPCRelative);
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bool isFPInstr(MachineInstr &MI);
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unsigned getRealRegNum(unsigned fakeReg, unsigned regClass,
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MachineInstr &MI);
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};
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#endif
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