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Fix the encoding of the armv7m (MClass) for MSR registers other than aspr,

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iaspr, espr and xpsr which also needed to have 0b10 in their mask encoding bits.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158560 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kevin Enderby
2012-06-15 22:14:44 +00:00
parent 307473dec0
commit f49a4092bc
3 changed files with 41 additions and 31 deletions
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30
lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
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@@ -671,16 +671,26 @@ void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
case 0x803: O << "xpsr"; return; // with _nzcvq bits is an alias for xpsr
case 0x403: O << "xpsr_g"; return;
case 0xc03: O << "xpsr_nzcvqg"; return;
case 5: O << "ipsr"; return;
case 6: O << "epsr"; return;
case 7: O << "iepsr"; return;
case 8: O << "msp"; return;
case 9: O << "psp"; return;
case 16: O << "primask"; return;
case 17: O << "basepri"; return;
case 18: O << "basepri_max"; return;
case 19: O << "faultmask"; return;
case 20: O << "control"; return;
case 5:
case 0x805: O << "ipsr"; return;
case 6:
case 0x806: O << "epsr"; return;
case 7:
case 0x807: O << "iepsr"; return;
case 8:
case 0x808: O << "msp"; return;
case 9:
case 0x809: O << "psp"; return;
case 0x10:
case 0x810: O << "primask"; return;
case 0x11:
case 0x811: O << "basepri"; return;
case 0x12:
case 0x812: O << "basepri_max"; return;
case 0x13:
case 0x813: O << "faultmask"; return;
case 0x14:
case 0x814: O << "control"; return;
}
}