6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-09-30 19:55:11 +00:00
Code Issues Projects Releases Wiki Activity

ARM64: remove dead validation code from the AsmParser.

Browse Source 
If this code triggers, any immediate has already been validated so it can't
possibly trigger a diagnostic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208564 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover 2014-05-12 14:13:21 +00:00
parent f8c7bd4696
commit f502ba6e78
1 changed files with 0 additions and 198 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

198
lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
View File

@ -3604,204 +3604,6 @@ bool ARM64AsmParser::validateInstruction(MCInst &Inst,
}
return false;
}
case ARM64::LDRBpre:
case ARM64::LDRHpre:
case ARM64::LDRSBWpre:
case ARM64::LDRSBXpre:
case ARM64::LDRSHWpre:
case ARM64::LDRSHXpre:
case ARM64::LDRWpre:
case ARM64::LDRXpre:
case ARM64::LDRSpre:
case ARM64::LDRDpre:
case ARM64::LDRQpre:
case ARM64::STRBpre:
case ARM64::STRHpre:
case ARM64::STRWpre:
case ARM64::STRXpre:
case ARM64::STRSpre:
case ARM64::STRDpre:
case ARM64::STRQpre:
case ARM64::LDRBpost:
case ARM64::LDRHpost:
case ARM64::LDRSBWpost:
case ARM64::LDRSBXpost:
case ARM64::LDRSHWpost:
case ARM64::LDRSHXpost:
case ARM64::LDRWpost:
case ARM64::LDRXpost:
case ARM64::LDRSpost:
case ARM64::LDRDpost:
case ARM64::LDRQpost:
case ARM64::STRBpost:
case ARM64::STRHpost:
case ARM64::STRWpost:
case ARM64::STRXpost:
case ARM64::STRSpost:
case ARM64::STRDpost:
case ARM64::STRQpost:
case ARM64::LDTRXi:
case ARM64::LDTRWi:
case ARM64::LDTRHi:
case ARM64::LDTRBi:
case ARM64::LDTRSHWi:
case ARM64::LDTRSHXi:
case ARM64::LDTRSBWi:
case ARM64::LDTRSBXi:
case ARM64::LDTRSWi:
case ARM64::STTRWi:
case ARM64::STTRXi:
case ARM64::STTRHi:
case ARM64::STTRBi:
case ARM64::LDURWi:
case ARM64::LDURXi:
case ARM64::LDURSi:
case ARM64::LDURDi:
case ARM64::LDURQi:
case ARM64::LDURHi:
case ARM64::LDURBi:
case ARM64::LDURSHWi:
case ARM64::LDURSHXi:
case ARM64::LDURSBWi:
case ARM64::LDURSBXi:
case ARM64::LDURSWi:
case ARM64::PRFUMi:
case ARM64::STURWi:
case ARM64::STURXi:
case ARM64::STURSi:
case ARM64::STURDi:
case ARM64::STURQi:
case ARM64::STURHi:
case ARM64::STURBi: {
// FIXME: Should accept expressions and error in fixup evaluation
// if out of range.
if (!Inst.getOperand(2).isImm())
return Error(Loc[1], "immediate value expected");
int64_t offset = Inst.getOperand(2).getImm();
if (offset > 255 || offset < -256)
return Error(Loc[1], "offset value out of range");
return false;
}
case ARM64::LDRSro:
case ARM64::LDRWro:
case ARM64::LDRSWro:
case ARM64::STRWro:
case ARM64::STRSro: {
// FIXME: Should accept expressions and error in fixup evaluation
// if out of range.
if (!Inst.getOperand(3).isImm())
return Error(Loc[1], "immediate value expected");
int64_t shift = Inst.getOperand(3).getImm();
ARM64_AM::ShiftExtendType type = ARM64_AM::getMemExtendType(shift);
if (type != ARM64_AM::UXTW && type != ARM64_AM::UXTX &&
type != ARM64_AM::SXTW && type != ARM64_AM::SXTX)
return Error(Loc[1], "shift type invalid");
return false;
}
case ARM64::LDRDro:
case ARM64::LDRQro:
case ARM64::LDRXro:
case ARM64::PRFMro:
case ARM64::STRXro:
case ARM64::STRDro:
case ARM64::STRQro: {
// FIXME: Should accept expressions and error in fixup evaluation
// if out of range.
if (!Inst.getOperand(3).isImm())
return Error(Loc[1], "immediate value expected");
int64_t shift = Inst.getOperand(3).getImm();
ARM64_AM::ShiftExtendType type = ARM64_AM::getMemExtendType(shift);
if (type != ARM64_AM::UXTW && type != ARM64_AM::UXTX &&
type != ARM64_AM::SXTW && type != ARM64_AM::SXTX)
return Error(Loc[1], "shift type invalid");
return false;
}
case ARM64::LDRHro:
case ARM64::LDRHHro:
case ARM64::LDRSHWro:
case ARM64::LDRSHXro:
case ARM64::STRHro:
case ARM64::STRHHro: {
// FIXME: Should accept expressions and error in fixup evaluation
// if out of range.
if (!Inst.getOperand(3).isImm())
return Error(Loc[1], "immediate value expected");
int64_t shift = Inst.getOperand(3).getImm();
ARM64_AM::ShiftExtendType type = ARM64_AM::getMemExtendType(shift);
if (type != ARM64_AM::UXTW && type != ARM64_AM::UXTX &&
type != ARM64_AM::SXTW && type != ARM64_AM::SXTX)
return Error(Loc[1], "shift type invalid");
return false;
}
case ARM64::LDRBro:
case ARM64::LDRBBro:
case ARM64::LDRSBWro:
case ARM64::LDRSBXro:
case ARM64::STRBro:
case ARM64::STRBBro: {
// FIXME: Should accept expressions and error in fixup evaluation
// if out of range.
if (!Inst.getOperand(3).isImm())
return Error(Loc[1], "immediate value expected");
int64_t shift = Inst.getOperand(3).getImm();
ARM64_AM::ShiftExtendType type = ARM64_AM::getMemExtendType(shift);
if (type != ARM64_AM::UXTW && type != ARM64_AM::UXTX &&
type != ARM64_AM::SXTW && type != ARM64_AM::SXTX)
return Error(Loc[1], "shift type invalid");
return false;
}
case ARM64::LDPWi:
case ARM64::LDPXi:
case ARM64::LDPSi:
case ARM64::LDPDi:
case ARM64::LDPQi:
case ARM64::LDPSWi:
case ARM64::STPWi:
case ARM64::STPXi:
case ARM64::STPSi:
case ARM64::STPDi:
case ARM64::STPQi:
case ARM64::LDPWpre:
case ARM64::LDPXpre:
case ARM64::LDPSpre:
case ARM64::LDPDpre:
case ARM64::LDPQpre:
case ARM64::LDPSWpre:
case ARM64::STPWpre:
case ARM64::STPXpre:
case ARM64::STPSpre:
case ARM64::STPDpre:
case ARM64::STPQpre:
case ARM64::LDPWpost:
case ARM64::LDPXpost:
case ARM64::LDPSpost:
case ARM64::LDPDpost:
case ARM64::LDPQpost:
case ARM64::LDPSWpost:
case ARM64::STPWpost:
case ARM64::STPXpost:
case ARM64::STPSpost:
case ARM64::STPDpost:
case ARM64::STPQpost:
case ARM64::LDNPWi:
case ARM64::LDNPXi:
case ARM64::LDNPSi:
case ARM64::LDNPDi:
case ARM64::LDNPQi:
case ARM64::STNPWi:
case ARM64::STNPXi:
case ARM64::STNPSi:
case ARM64::STNPDi:
case ARM64::STNPQi: {
// FIXME: Should accept expressions and error in fixup evaluation
// if out of range.
if (!Inst.getOperand(3).isImm())
return Error(Loc[2], "immediate value expected");
int64_t offset = Inst.getOperand(3).getImm();
if (offset > 63 || offset < -64)
return Error(Loc[2], "offset value out of range");
return false;
}
default:
return false;
}