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R600: Use the same compute kernel calling convention for all GPUs
A side-effect of this is that now the compiler expects kernel arguments to be 4-byte aligned. Reviewed-by: Vincent Lejeune <vljn at ovi.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186916 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -36,9 +36,9 @@ def CC_SI : CallingConv<[
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]>;
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// Calling convention for SI compute kernels
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def CC_SI_Kernel : CallingConv<[
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CCIfType<[v4i32, v4f32], CCAssignToStack <16, 4>>,
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// Calling convention for compute kernels
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def CC_AMDGPU_Kernel : CallingConv<[
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CCIfType<[v4i32, v4f32], CCAssignToStack <16, 16>>,
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CCIfType<[i64, f64], CCAssignToStack < 8, 4>>,
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CCIfType<[i32, f32], CCAssignToStack < 4, 4>>,
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CCIfType<[i16], CCAssignToStack < 2, 4>>,
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@ -46,8 +46,14 @@ def CC_SI_Kernel : CallingConv<[
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]>;
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def CC_AMDGPU : CallingConv<[
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CCIf<"State.getMachineFunction().getInfo<SIMachineFunctionInfo>()->"#
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"ShaderType == ShaderType::COMPUTE", CCDelegateTo<CC_SI_Kernel>>,
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CCIf<"State.getTarget().getSubtarget<AMDGPUSubtarget>().getGeneration() == "
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"AMDGPUSubtarget::SOUTHERN_ISLANDS && "
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"State.getMachineFunction().getInfo<SIMachineFunctionInfo>()->"#
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"ShaderType == ShaderType::COMPUTE", CCDelegateTo<CC_AMDGPU_Kernel>>,
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CCIf<"State.getTarget().getSubtarget<AMDGPUSubtarget>().getGeneration() < "
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"AMDGPUSubtarget::SOUTHERN_ISLANDS && "
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"State.getMachineFunction().getInfo<R600MachineFunctionInfo>()->"
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"ShaderType == ShaderType::COMPUTE", CCDelegateTo<CC_AMDGPU_Kernel>>,
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CCIf<"State.getTarget().getSubtarget<AMDGPUSubtarget>()"#
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".getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS", CCDelegateTo<CC_SI>>
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]>;
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@ -18,6 +18,7 @@
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#include "AMDGPURegisterInfo.h"
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#include "AMDGPUSubtarget.h"
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#include "AMDILIntrinsicInfo.h"
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#include "R600MachineFunctionInfo.h"
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#include "SIMachineFunctionInfo.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineFunction.h"
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@ -16,6 +16,7 @@
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#include "R600Defines.h"
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#include "R600InstrInfo.h"
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#include "R600MachineFunctionInfo.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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@ -1212,11 +1213,17 @@ SDValue R600TargetLowering::LowerFormalArguments(
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const SmallVectorImpl<ISD::InputArg> &Ins,
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SDLoc DL, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const {
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unsigned ParamOffsetBytes = 36;
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
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getTargetMachine(), ArgLocs, *DAG.getContext());
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AnalyzeFormalArguments(CCInfo, Ins);
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Function::const_arg_iterator FuncArg =
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DAG.getMachineFunction().getFunction()->arg_begin();
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for (unsigned i = 0, e = Ins.size(); i < e; ++i, ++FuncArg) {
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EVT VT = Ins[i].VT;
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CCValAssign &VA = ArgLocs[i];
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EVT VT = VA.getLocVT();
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Type *ArgType = FuncArg->getType();
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unsigned ArgSizeInBits = ArgType->isPointerTy() ?
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32 : ArgType->getPrimitiveSizeInBits();
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@ -1239,12 +1246,14 @@ SDValue R600TargetLowering::LowerFormalArguments(
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PointerType *PtrTy = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
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AMDGPUAS::PARAM_I_ADDRESS);
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// The first 36 bytes of the input buffer contains information about
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// thread group and global sizes.
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SDValue Arg = DAG.getExtLoad(LoadType, DL, VT, DAG.getRoot(),
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DAG.getConstant(ParamOffsetBytes, MVT::i32),
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MachinePointerInfo(UndefValue::get(PtrTy)),
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ArgVT, false, false, ArgBytes);
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DAG.getConstant(36 + VA.getLocMemOffset(), MVT::i32),
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MachinePointerInfo(UndefValue::get(PtrTy)),
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ArgVT, false, false, ArgBytes);
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InVals.push_back(Arg);
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ParamOffsetBytes += ArgBytes;
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}
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return Chain;
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}
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@ -2,7 +2,7 @@
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; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK
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; R600-CHECK: @v4i32_kernel_arg
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; R600-CHECK: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 40
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; R600-CHECK: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 52
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; SI-CHECK: @v4i32_kernel_arg
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; SI-CHECK: BUFFER_STORE_DWORDX4
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define void @v4i32_kernel_arg(<4 x i32> addrspace(1)* %out, <4 x i32> %in) {
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@ -12,7 +12,7 @@ entry:
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}
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; R600-CHECK: @v4f32_kernel_arg
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; R600-CHECK: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 40
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; R600-CHECK: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 52
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; SI-CHECK: @v4f32_kernel_arg
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; SI-CHECK: BUFFER_STORE_DWORDX4
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define void @v4f32_kernel_args(<4 x float> addrspace(1)* %out, <4 x float> %in) {
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