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https://github.com/c64scene-ar/llvm-6502.git
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Make isOperationLegal do what its name suggests, and introduce a
new isOperationLegalOrCustom, which does what isOperationLegal previously did. Update a bunch of callers to use isOperationLegalOrCustom instead of isOperationLegal. In some case it wasn't obvious which behavior is desired; when in doubt I changed then to isOperationLegalOrCustom as that preserves their previous behavior. This is for the second half of PR3376. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63212 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -340,12 +340,20 @@ public:
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return (LegalizeAction)((OpActions[Op] >> (2*VT.getSimpleVT())) & 3);
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}
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/// isOperationLegalOrCustom - Return true if the specified operation is
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/// legal on this target or can be made legal with custom lowering. This
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/// is used to help guide high-level lowering decisions.
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bool isOperationLegalOrCustom(unsigned Op, MVT VT) const {
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return (VT == MVT::Other || isTypeLegal(VT)) &&
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(getOperationAction(Op, VT) == Legal ||
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getOperationAction(Op, VT) == Custom);
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}
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/// isOperationLegal - Return true if the specified operation is legal on this
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/// target.
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bool isOperationLegal(unsigned Op, MVT VT) const {
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return (VT == MVT::Other || isTypeLegal(VT)) &&
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(getOperationAction(Op, VT) == Legal ||
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getOperationAction(Op, VT) == Custom);
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getOperationAction(Op, VT) == Legal;
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}
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/// getLoadExtAction - Return how this load with extension should be treated:
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@ -2054,8 +2054,8 @@ SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS) {
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if (!TLI.isTypeLegal(VT)) return 0;
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// The target must have at least one rotate flavor.
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bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT);
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bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT);
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bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
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bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
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if (!HasROTL && !HasROTR) return 0;
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// Match "(X shl/srl V1) & V2" where V2 may not be present.
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@ -2541,8 +2541,8 @@ SDValue DAGCombiner::visitSRA(SDNode *N) {
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// on that type, and the the truncate to that type is both legal and free,
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// perform the transform.
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if (ShiftAmt &&
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TLI.isOperationLegal(ISD::SIGN_EXTEND, TruncVT) &&
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TLI.isOperationLegal(ISD::TRUNCATE, VT) &&
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TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
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TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
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TLI.isTruncateFree(VT, TruncVT)) {
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SDValue Amt = DAG.getConstant(ShiftAmt, TLI.getShiftAmountTy());
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@ -2795,7 +2795,7 @@ SDValue DAGCombiner::visitSELECT(SDNode *N) {
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// Check against MVT::Other for SELECT_CC, which is a workaround for targets
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// having to say they don't support SELECT_CC on every type the DAG knows
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// about, since there is no way to mark an opcode illegal at all value types
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if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other))
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if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other))
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return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1),
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N1, N2, N0.getOperand(2));
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else
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@ -4032,8 +4032,8 @@ SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
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// If the input is a legal type, and SINT_TO_FP is not legal on this target,
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// but UINT_TO_FP is legal on this target, try to convert.
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if (!TLI.isOperationLegal(ISD::SINT_TO_FP, OpVT) &&
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TLI.isOperationLegal(ISD::UINT_TO_FP, OpVT)) {
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if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) &&
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TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) {
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// If the sign bit is known to be zero, we can change this to UINT_TO_FP.
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if (DAG.SignBitIsZero(N0))
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return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
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@ -4055,8 +4055,8 @@ SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
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// If the input is a legal type, and UINT_TO_FP is not legal on this target,
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// but SINT_TO_FP is legal on this target, try to convert.
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if (!TLI.isOperationLegal(ISD::UINT_TO_FP, OpVT) &&
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TLI.isOperationLegal(ISD::SINT_TO_FP, OpVT)) {
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if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) &&
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TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) {
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// If the sign bit is known to be zero, we can change this to SINT_TO_FP.
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if (DAG.SignBitIsZero(N0))
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return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
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@ -4252,7 +4252,7 @@ SDValue DAGCombiner::visitBRCOND(SDNode *N) {
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// fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
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// on the target.
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if (N1.getOpcode() == ISD::SETCC &&
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TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) {
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TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) {
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return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2),
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N1.getOperand(0), N1.getOperand(1), N2);
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}
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@ -4726,7 +4726,7 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) {
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getABITypeAlignment(SVT.getTypeForMVT());
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if (Align <= OrigAlign &&
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((!LegalOperations && !ST->isVolatile()) ||
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TLI.isOperationLegal(ISD::STORE, SVT)))
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TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
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return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(),
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ST->getSrcValueOffset(), ST->isVolatile(), OrigAlign);
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}
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@ -4747,7 +4747,8 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) {
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break;
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case MVT::f32:
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if (((TLI.isTypeLegal(MVT::i32) || !LegalTypes) && !LegalOperations &&
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!ST->isVolatile()) || TLI.isOperationLegal(ISD::STORE, MVT::i32)) {
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!ST->isVolatile()) ||
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TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
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Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
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bitcastToAPInt().getZExtValue(), MVT::i32);
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return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
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@ -4757,14 +4758,15 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) {
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break;
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case MVT::f64:
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if (((TLI.isTypeLegal(MVT::i64) || !LegalTypes) && !LegalOperations &&
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!ST->isVolatile()) || TLI.isOperationLegal(ISD::STORE, MVT::i64)) {
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!ST->isVolatile()) ||
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TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
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Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
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getZExtValue(), MVT::i64);
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return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
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ST->getSrcValueOffset(), ST->isVolatile(),
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ST->getAlignment());
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} else if (!ST->isVolatile() &&
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TLI.isOperationLegal(ISD::STORE, MVT::i32)) {
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TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
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// Many FP stores are not made apparent until after legalize, e.g. for
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// argument passing. Since this is so common, custom legalize the
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// 64-bit integer store into two 32-bit stores.
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@ -4967,7 +4969,7 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
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// original load.
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unsigned NewAlign = TLI.getTargetData()->
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getABITypeAlignment(LVT.getTypeForMVT());
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if (NewAlign > Align || !TLI.isOperationLegal(ISD::LOAD, LVT))
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if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT))
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return SDValue();
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Align = NewAlign;
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}
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@ -1263,8 +1263,9 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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default: assert(0 && "This action is not supported yet!");
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case TargetLowering::Expand: {
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DwarfWriter *DW = DAG.getDwarfWriter();
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bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
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bool useLABEL = TLI.isOperationLegal(ISD::DBG_LABEL, MVT::Other);
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bool useDEBUG_LOC = TLI.isOperationLegalOrCustom(ISD::DEBUG_LOC,
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MVT::Other);
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bool useLABEL = TLI.isOperationLegalOrCustom(ISD::DBG_LABEL, MVT::Other);
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const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node);
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GlobalVariable *CU_GV = cast<GlobalVariable>(DSP->getCompileUnit());
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@ -3065,7 +3066,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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"Fell off of the edge of the floating point world");
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// If the target supports SETCC of this type, use it.
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if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
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if (TLI.isOperationLegalOrCustom(ISD::SETCC, NewInTy))
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break;
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}
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if (NewInTy.isInteger())
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@ -3228,10 +3229,10 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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// and unsigned forms. If the target supports both SMUL_LOHI and
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// UMUL_LOHI, form a preference by checking which forms of plain
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// MULH it supports.
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bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT);
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bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT);
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bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT);
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bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT);
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bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
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bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
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bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
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bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
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unsigned OpToUse = 0;
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if (HasSMUL_LOHI && !HasMULHS) {
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OpToUse = ISD::SMUL_LOHI;
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@ -3248,25 +3249,25 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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}
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}
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if (Node->getOpcode() == ISD::MULHS &&
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TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
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TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) {
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Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).getNode(),
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1);
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break;
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}
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if (Node->getOpcode() == ISD::MULHU &&
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TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
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TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) {
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Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).getNode(),
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1);
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break;
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}
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if (Node->getOpcode() == ISD::SDIV &&
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TLI.isOperationLegal(ISD::SDIVREM, VT)) {
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TLI.isOperationLegalOrCustom(ISD::SDIVREM, VT)) {
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Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(),
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0);
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break;
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}
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if (Node->getOpcode() == ISD::UDIV &&
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TLI.isOperationLegal(ISD::UDIVREM, VT)) {
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TLI.isOperationLegalOrCustom(ISD::UDIVREM, VT)) {
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Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(),
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0);
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break;
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@ -3510,12 +3511,12 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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// See if remainder can be lowered using two-result operations.
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SDVTList VTs = DAG.getVTList(VT, VT);
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if (Node->getOpcode() == ISD::SREM &&
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TLI.isOperationLegal(ISD::SDIVREM, VT)) {
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TLI.isOperationLegalOrCustom(ISD::SDIVREM, VT)) {
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Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(), 1);
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break;
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}
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if (Node->getOpcode() == ISD::UREM &&
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TLI.isOperationLegal(ISD::UDIVREM, VT)) {
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TLI.isOperationLegalOrCustom(ISD::UDIVREM, VT)) {
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Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(), 1);
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break;
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}
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@ -4639,8 +4640,8 @@ SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) {
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// FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
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// legal, such as PowerPC.
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if (Node->getOpcode() == ISD::FP_TO_UINT &&
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!TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
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(TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
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!TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NVT) &&
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(TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT) ||
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TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
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Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
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} else {
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@ -5549,7 +5550,8 @@ SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
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&MaskVec[0], MaskVec.size());
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// If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it.
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if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
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if (TLI.isOperationLegalOrCustom(ISD::SCALAR_TO_VECTOR,
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Node->getValueType(0)) &&
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isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
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Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val1);
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Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val2);
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@ -6330,8 +6332,8 @@ SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op) {
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SDValue Tmp3 = DAG.getNode(ISD::AND, VT, DAG.getNOT(Op, VT),
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DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
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// If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
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if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
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TLI.isOperationLegal(ISD::CTLZ, VT))
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if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
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TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
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return DAG.getNode(ISD::SUB, VT,
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DAG.getConstant(VT.getSizeInBits(), VT),
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DAG.getNode(ISD::CTLZ, VT, Tmp3));
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@ -6821,8 +6823,9 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
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// If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
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// this X << 1 as X+X.
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if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
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if (ShAmt->getAPIntValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
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TLI.isOperationLegal(ISD::ADDE, NVT)) {
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if (ShAmt->getAPIntValue() == 1 &&
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TLI.isOperationLegalOrCustom(ISD::ADDC, NVT) &&
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TLI.isOperationLegalOrCustom(ISD::ADDE, NVT)) {
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SDValue LoOps[2], HiOps[3];
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ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
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SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
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@ -6944,7 +6947,7 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
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bool hasCarry = false;
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for (unsigned BitSize = NVT.getSizeInBits(); BitSize != 0; BitSize /= 2) {
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MVT AVT = MVT::getIntegerVT(BitSize);
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if (TLI.isOperationLegal(OpV, AVT)) {
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if (TLI.isOperationLegalOrCustom(OpV, AVT)) {
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hasCarry = true;
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break;
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}
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@ -7041,10 +7044,10 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
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}
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}
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bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
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bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
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bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
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bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
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bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
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bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT);
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bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT);
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bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT);
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if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
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SDValue LL, LH, RL, RH;
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ExpandOp(Node->getOperand(0), LL, LH);
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@ -345,8 +345,8 @@ SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
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// FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
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// legal, such as PowerPC.
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if (N->getOpcode() == ISD::FP_TO_UINT &&
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!TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
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TLI.isOperationLegal(ISD::FP_TO_SINT, NVT))
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!TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NVT) &&
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TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
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NewOpc = ISD::FP_TO_SINT;
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SDValue Res = DAG.getNode(NewOpc, NVT, N->getOperand(0));
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@ -1008,7 +1008,8 @@ void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
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Lo = DAG.getConstant(0, NVT);
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Hi = InL;
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} else if (Amt == 1 &&
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TLI.isOperationLegal(ISD::ADDC, TLI.getTypeToExpandTo(NVT))) {
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TLI.isOperationLegalOrCustom(ISD::ADDC,
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TLI.getTypeToExpandTo(NVT))) {
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// Emit this X << 1 as X+X.
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SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
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SDValue LoOps[2] = { InL, InL };
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@ -1166,8 +1167,9 @@ void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
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// a carry of type MVT::Flag, but there doesn't seem to be any way to
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// generate a value of this type in the expanded code sequence.
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bool hasCarry =
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TLI.isOperationLegal(N->getOpcode() == ISD::ADD ? ISD::ADDC : ISD::SUBC,
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TLI.getTypeToExpandTo(NVT));
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TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
|
||||
ISD::ADDC : ISD::SUBC,
|
||||
TLI.getTypeToExpandTo(NVT));
|
||||
|
||||
if (hasCarry) {
|
||||
SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
|
||||
@ -1513,10 +1515,10 @@ void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
|
||||
MVT VT = N->getValueType(0);
|
||||
MVT NVT = TLI.getTypeToTransformTo(VT);
|
||||
|
||||
bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
|
||||
bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
|
||||
bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
|
||||
bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
|
||||
bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
|
||||
bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT);
|
||||
bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT);
|
||||
bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT);
|
||||
if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
|
||||
SDValue LL, LH, RL, RH;
|
||||
GetExpandedInteger(N->getOperand(0), LL, LH);
|
||||
|
@ -1588,8 +1588,8 @@ bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR,
|
||||
|
||||
static inline bool areJTsAllowed(const TargetLowering &TLI) {
|
||||
return !DisableJumpTables &&
|
||||
(TLI.isOperationLegal(ISD::BR_JT, MVT::Other) ||
|
||||
TLI.isOperationLegal(ISD::BRIND, MVT::Other));
|
||||
(TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
|
||||
TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
|
||||
}
|
||||
|
||||
static APInt ComputeRange(const APInt &First, const APInt &Last) {
|
||||
|
@ -2365,10 +2365,10 @@ SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
|
||||
// Multiply the numerator (operand 0) by the magic value
|
||||
// FIXME: We should support doing a MUL in a wider type
|
||||
SDValue Q;
|
||||
if (isOperationLegal(ISD::MULHS, VT))
|
||||
if (isOperationLegalOrCustom(ISD::MULHS, VT))
|
||||
Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0),
|
||||
DAG.getConstant(magics.m, VT));
|
||||
else if (isOperationLegal(ISD::SMUL_LOHI, VT))
|
||||
else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
|
||||
Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(VT, VT),
|
||||
N->getOperand(0),
|
||||
DAG.getConstant(magics.m, VT)).getNode(), 1);
|
||||
@ -2423,10 +2423,10 @@ SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
|
||||
// Multiply the numerator (operand 0) by the magic value
|
||||
// FIXME: We should support doing a MUL in a wider type
|
||||
SDValue Q;
|
||||
if (isOperationLegal(ISD::MULHU, VT))
|
||||
if (isOperationLegalOrCustom(ISD::MULHU, VT))
|
||||
Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0),
|
||||
DAG.getConstant(magics.m, VT));
|
||||
else if (isOperationLegal(ISD::UMUL_LOHI, VT))
|
||||
else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
|
||||
Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(VT, VT),
|
||||
N->getOperand(0),
|
||||
DAG.getConstant(magics.m, VT)).getNode(), 1);
|
||||
|
Loading…
Reference in New Issue
Block a user