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ARM: Tidy up IntrinsicsARM.td a bit.

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Make the TargetPrefix setting one big setting instead of being spread out
everywhere. No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164265 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2012-09-19 23:39:03 +00:00
parent e853d2e250
commit f5958e9dea
1 changed files with 199 additions and 217 deletions
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416
include/llvm/IntrinsicsARM.td
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@@ -16,147 +16,136 @@
// TLS // TLS
let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.". let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
def int_arm_thread_pointer : GCCBuiltin<"__builtin_thread_pointer">,
Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>; def int_arm_thread_pointer : GCCBuiltin<"__builtin_thread_pointer">,
} Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Saturating Arithmentic // Saturating Arithmentic
let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.". def int_arm_qadd : GCCBuiltin<"__builtin_arm_qadd">,
def int_arm_qadd : GCCBuiltin<"__builtin_arm_qadd">, Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem, Commutative]>;
[IntrNoMem, Commutative]>; def int_arm_qsub : GCCBuiltin<"__builtin_arm_qsub">,
def int_arm_qsub : GCCBuiltin<"__builtin_arm_qsub">, Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; def int_arm_ssat : GCCBuiltin<"__builtin_arm_ssat">,
def int_arm_ssat : GCCBuiltin<"__builtin_arm_ssat">, Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; def int_arm_usat : GCCBuiltin<"__builtin_arm_usat">,
def int_arm_usat : GCCBuiltin<"__builtin_arm_usat">, Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Load and Store exclusive doubleword // Load and Store exclusive doubleword
let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.". def int_arm_strexd : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,
def int_arm_strexd : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], [IntrReadWriteArgMem]>;
llvm_ptr_ty], [IntrReadWriteArgMem]>; def int_arm_ldrexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty],
def int_arm_ldrexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty], [IntrReadArgMem]>;
[IntrReadArgMem]>;
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// VFP // VFP
let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.". def int_arm_get_fpscr : GCCBuiltin<"__builtin_arm_get_fpscr">,
def int_arm_get_fpscr : GCCBuiltin<"__builtin_arm_get_fpscr">, Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>;
Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>; def int_arm_set_fpscr : GCCBuiltin<"__builtin_arm_set_fpscr">,
def int_arm_set_fpscr : GCCBuiltin<"__builtin_arm_set_fpscr">, Intrinsic<[], [llvm_i32_ty], []>;
Intrinsic<[], [llvm_i32_ty], []>; def int_arm_vcvtr : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
def int_arm_vcvtr : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty], [IntrNoMem]>;
[IntrNoMem]>; def int_arm_vcvtru : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
def int_arm_vcvtru : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty], [IntrNoMem]>;
[IntrNoMem]>;
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Coprocessor // Coprocessor
let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.". // Move to coprocessor
// Move to coprocessor def int_arm_mcr : GCCBuiltin<"__builtin_arm_mcr">,
def int_arm_mcr : GCCBuiltin<"__builtin_arm_mcr">, Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>; def int_arm_mcr2 : GCCBuiltin<"__builtin_arm_mcr2">,
def int_arm_mcr2 : GCCBuiltin<"__builtin_arm_mcr2">, Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
// Move from coprocessor // Move from coprocessor
def int_arm_mrc : GCCBuiltin<"__builtin_arm_mrc">, def int_arm_mrc : GCCBuiltin<"__builtin_arm_mrc">,
Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
llvm_i32_ty, llvm_i32_ty], []>; llvm_i32_ty, llvm_i32_ty], []>;
def int_arm_mrc2 : GCCBuiltin<"__builtin_arm_mrc2">, def int_arm_mrc2 : GCCBuiltin<"__builtin_arm_mrc2">,
Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
llvm_i32_ty, llvm_i32_ty], []>; llvm_i32_ty, llvm_i32_ty], []>;
// Coprocessor data processing // Coprocessor data processing
def int_arm_cdp : GCCBuiltin<"__builtin_arm_cdp">, def int_arm_cdp : GCCBuiltin<"__builtin_arm_cdp">,
Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>; llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
def int_arm_cdp2 : GCCBuiltin<"__builtin_arm_cdp2">, def int_arm_cdp2 : GCCBuiltin<"__builtin_arm_cdp2">,
Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>; llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
// Move from two registers to coprocessor // Move from two registers to coprocessor
def int_arm_mcrr : GCCBuiltin<"__builtin_arm_mcrr">, def int_arm_mcrr : GCCBuiltin<"__builtin_arm_mcrr">,
Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
llvm_i32_ty, llvm_i32_ty], []>; llvm_i32_ty, llvm_i32_ty], []>;
def int_arm_mcrr2 : GCCBuiltin<"__builtin_arm_mcrr2">, def int_arm_mcrr2 : GCCBuiltin<"__builtin_arm_mcrr2">,
Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
llvm_i32_ty, llvm_i32_ty], []>; llvm_i32_ty, llvm_i32_ty], []>;
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Advanced SIMD (NEON) // Advanced SIMD (NEON)
let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.". // The following classes do not correspond directly to GCC builtins.
class Neon_1Arg_Intrinsic
: Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
class Neon_1Arg_Narrow_Intrinsic
: Intrinsic<[llvm_anyvector_ty],
[LLVMExtendedElementVectorType<0>], [IntrNoMem]>;
class Neon_2Arg_Intrinsic
: Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
[IntrNoMem]>;
class Neon_2Arg_Narrow_Intrinsic
: Intrinsic<[llvm_anyvector_ty],
[LLVMExtendedElementVectorType<0>,
LLVMExtendedElementVectorType<0>],
[IntrNoMem]>;
class Neon_2Arg_Long_Intrinsic
: Intrinsic<[llvm_anyvector_ty],
[LLVMTruncatedElementVectorType<0>,
LLVMTruncatedElementVectorType<0>],
[IntrNoMem]>;
class Neon_3Arg_Intrinsic
: Intrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
[IntrNoMem]>;
class Neon_3Arg_Long_Intrinsic
: Intrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>,
LLVMTruncatedElementVectorType<0>,
LLVMTruncatedElementVectorType<0>],
[IntrNoMem]>;
class Neon_CvtFxToFP_Intrinsic
: Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
class Neon_CvtFPToFx_Intrinsic
: Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>;
// The following classes do not correspond directly to GCC builtins. // The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors.
class Neon_1Arg_Intrinsic // Besides the table, VTBL has one other v8i8 argument and VTBX has two.
: Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>; // Overall, the classes range from 2 to 6 v8i8 arguments.
class Neon_1Arg_Narrow_Intrinsic class Neon_Tbl2Arg_Intrinsic
: Intrinsic<[llvm_anyvector_ty], : Intrinsic<[llvm_v8i8_ty],
[LLVMExtendedElementVectorType<0>], [IntrNoMem]>; [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
class Neon_2Arg_Intrinsic class Neon_Tbl3Arg_Intrinsic
: Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>], : Intrinsic<[llvm_v8i8_ty],
[IntrNoMem]>; [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
class Neon_2Arg_Narrow_Intrinsic class Neon_Tbl4Arg_Intrinsic
: Intrinsic<[llvm_anyvector_ty], : Intrinsic<[llvm_v8i8_ty],
[LLVMExtendedElementVectorType<0>, [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty],
LLVMExtendedElementVectorType<0>], [IntrNoMem]>;
[IntrNoMem]>; class Neon_Tbl5Arg_Intrinsic
class Neon_2Arg_Long_Intrinsic : Intrinsic<[llvm_v8i8_ty],
: Intrinsic<[llvm_anyvector_ty], [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
[LLVMTruncatedElementVectorType<0>, llvm_v8i8_ty], [IntrNoMem]>;
LLVMTruncatedElementVectorType<0>], class Neon_Tbl6Arg_Intrinsic
[IntrNoMem]>; : Intrinsic<[llvm_v8i8_ty],
class Neon_3Arg_Intrinsic [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
: Intrinsic<[llvm_anyvector_ty], llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
[IntrNoMem]>;
class Neon_3Arg_Long_Intrinsic
: Intrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>,
LLVMTruncatedElementVectorType<0>,
LLVMTruncatedElementVectorType<0>],
[IntrNoMem]>;
class Neon_CvtFxToFP_Intrinsic
: Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
class Neon_CvtFPToFx_Intrinsic
: Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>;
// The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors.
// Besides the table, VTBL has one other v8i8 argument and VTBX has two.
// Overall, the classes range from 2 to 6 v8i8 arguments.
class Neon_Tbl2Arg_Intrinsic
: Intrinsic<[llvm_v8i8_ty],
[llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
class Neon_Tbl3Arg_Intrinsic
: Intrinsic<[llvm_v8i8_ty],
[llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
class Neon_Tbl4Arg_Intrinsic
: Intrinsic<[llvm_v8i8_ty],
[llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty],
[IntrNoMem]>;
class Neon_Tbl5Arg_Intrinsic
: Intrinsic<[llvm_v8i8_ty],
[llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
llvm_v8i8_ty], [IntrNoMem]>;
class Neon_Tbl6Arg_Intrinsic
: Intrinsic<[llvm_v8i8_ty],
[llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
}
// Arithmetic ops // Arithmetic ops
@@ -209,20 +198,18 @@ def int_arm_neon_vsubhn : Neon_2Arg_Narrow_Intrinsic;
def int_arm_neon_vrsubhn : Neon_2Arg_Narrow_Intrinsic; def int_arm_neon_vrsubhn : Neon_2Arg_Narrow_Intrinsic;
// Vector Absolute Compare. // Vector Absolute Compare.
let TargetPrefix = "arm" in { def int_arm_neon_vacged : Intrinsic<[llvm_v2i32_ty],
def int_arm_neon_vacged : Intrinsic<[llvm_v2i32_ty], [llvm_v2f32_ty, llvm_v2f32_ty],
[llvm_v2f32_ty, llvm_v2f32_ty], [IntrNoMem]>;
[IntrNoMem]>; def int_arm_neon_vacgeq : Intrinsic<[llvm_v4i32_ty],
def int_arm_neon_vacgeq : Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty],
[llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;
[IntrNoMem]>; def int_arm_neon_vacgtd : Intrinsic<[llvm_v2i32_ty],
def int_arm_neon_vacgtd : Intrinsic<[llvm_v2i32_ty], [llvm_v2f32_ty, llvm_v2f32_ty],
[llvm_v2f32_ty, llvm_v2f32_ty], [IntrNoMem]>;
[IntrNoMem]>; def int_arm_neon_vacgtq : Intrinsic<[llvm_v4i32_ty],
def int_arm_neon_vacgtq : Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty],
[llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;
[IntrNoMem]>;
}
// Vector Absolute Differences. // Vector Absolute Differences.
def int_arm_neon_vabds : Neon_2Arg_Intrinsic; def int_arm_neon_vabds : Neon_2Arg_Intrinsic;
@@ -235,24 +222,20 @@ def int_arm_neon_vpadd : Neon_2Arg_Intrinsic;
// Note: This is different than the other "long" NEON intrinsics because // Note: This is different than the other "long" NEON intrinsics because
// the result vector has half as many elements as the source vector. // the result vector has half as many elements as the source vector.
// The source and destination vector types must be specified separately. // The source and destination vector types must be specified separately.
let TargetPrefix = "arm" in { def int_arm_neon_vpaddls : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
def int_arm_neon_vpaddls : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
[IntrNoMem]>; def int_arm_neon_vpaddlu : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
def int_arm_neon_vpaddlu : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
[IntrNoMem]>;
}
// Vector Pairwise Add and Accumulate Long. // Vector Pairwise Add and Accumulate Long.
// Note: This is similar to vpaddl but the destination vector also appears // Note: This is similar to vpaddl but the destination vector also appears
// as the first argument. // as the first argument.
let TargetPrefix = "arm" in { def int_arm_neon_vpadals : Intrinsic<[llvm_anyvector_ty],
def int_arm_neon_vpadals : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_anyvector_ty], [IntrNoMem]>;
[IntrNoMem]>; def int_arm_neon_vpadalu : Intrinsic<[llvm_anyvector_ty],
def int_arm_neon_vpadalu : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_anyvector_ty], [IntrNoMem]>;
[IntrNoMem]>;
}
// Vector Pairwise Maximum and Minimum. // Vector Pairwise Maximum and Minimum.
def int_arm_neon_vpmaxs : Neon_2Arg_Intrinsic; def int_arm_neon_vpmaxs : Neon_2Arg_Intrinsic;
@@ -364,79 +347,78 @@ def int_arm_neon_vtbx2 : Neon_Tbl4Arg_Intrinsic;
def int_arm_neon_vtbx3 : Neon_Tbl5Arg_Intrinsic; def int_arm_neon_vtbx3 : Neon_Tbl5Arg_Intrinsic;
def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic; def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic;
let TargetPrefix = "arm" in { // De-interleaving vector loads from N-element structures.
// Source operands are the address and alignment.
def int_arm_neon_vld1 : Intrinsic<[llvm_anyvector_ty],
[llvm_ptr_ty, llvm_i32_ty],
[IntrReadArgMem]>;
def int_arm_neon_vld2 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
[llvm_ptr_ty, llvm_i32_ty],
[IntrReadArgMem]>;
def int_arm_neon_vld3 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
LLVMMatchType<0>],
[llvm_ptr_ty, llvm_i32_ty],
[IntrReadArgMem]>;
def int_arm_neon_vld4 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
LLVMMatchType<0>, LLVMMatchType<0>],
[llvm_ptr_ty, llvm_i32_ty],
[IntrReadArgMem]>;
// De-interleaving vector loads from N-element structures. // Vector load N-element structure to one lane.
// Source operands are the address and alignment. // Source operands are: the address, the N input vectors (since only one
def int_arm_neon_vld1 : Intrinsic<[llvm_anyvector_ty], // lane is assigned), the lane number, and the alignment.
[llvm_ptr_ty, llvm_i32_ty], def int_arm_neon_vld2lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
[IntrReadArgMem]>; [llvm_ptr_ty, LLVMMatchType<0>,
def int_arm_neon_vld2 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>], LLVMMatchType<0>, llvm_i32_ty,
[llvm_ptr_ty, llvm_i32_ty], llvm_i32_ty], [IntrReadArgMem]>;
[IntrReadArgMem]>; def int_arm_neon_vld3lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
def int_arm_neon_vld3 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>],
LLVMMatchType<0>], [llvm_ptr_ty, LLVMMatchType<0>,
[llvm_ptr_ty, llvm_i32_ty], LLVMMatchType<0>, LLVMMatchType<0>,
[IntrReadArgMem]>; llvm_i32_ty, llvm_i32_ty],
def int_arm_neon_vld4 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, [IntrReadArgMem]>;
LLVMMatchType<0>, LLVMMatchType<0>], def int_arm_neon_vld4lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
[llvm_ptr_ty, llvm_i32_ty], LLVMMatchType<0>, LLVMMatchType<0>],
[IntrReadArgMem]>; [llvm_ptr_ty, LLVMMatchType<0>,
LLVMMatchType<0>, LLVMMatchType<0>,
LLVMMatchType<0>, llvm_i32_ty,
llvm_i32_ty], [IntrReadArgMem]>;
// Vector load N-element structure to one lane. // Interleaving vector stores from N-element structures.
// Source operands are: the address, the N input vectors (since only one // Source operands are: the address, the N vectors, and the alignment.
// lane is assigned), the lane number, and the alignment. def int_arm_neon_vst1 : Intrinsic<[],
def int_arm_neon_vld2lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>], [llvm_ptr_ty, llvm_anyvector_ty,
[llvm_ptr_ty, LLVMMatchType<0>, llvm_i32_ty], [IntrReadWriteArgMem]>;
LLVMMatchType<0>, llvm_i32_ty, def int_arm_neon_vst2 : Intrinsic<[],
llvm_i32_ty], [IntrReadArgMem]>; [llvm_ptr_ty, llvm_anyvector_ty,
def int_arm_neon_vld3lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty],
LLVMMatchType<0>], [IntrReadWriteArgMem]>;
[llvm_ptr_ty, LLVMMatchType<0>, def int_arm_neon_vst3 : Intrinsic<[],
LLVMMatchType<0>, LLVMMatchType<0>, [llvm_ptr_ty, llvm_anyvector_ty,
llvm_i32_ty, llvm_i32_ty], LLVMMatchType<0>, LLVMMatchType<0>,
[IntrReadArgMem]>; llvm_i32_ty], [IntrReadWriteArgMem]>;
def int_arm_neon_vld4lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, def int_arm_neon_vst4 : Intrinsic<[],
LLVMMatchType<0>, LLVMMatchType<0>], [llvm_ptr_ty, llvm_anyvector_ty,
[llvm_ptr_ty, LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>,
LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty],
LLVMMatchType<0>, llvm_i32_ty, [IntrReadWriteArgMem]>;
llvm_i32_ty], [IntrReadArgMem]>;
// Interleaving vector stores from N-element structures. // Vector store N-element structure from one lane.
// Source operands are: the address, the N vectors, and the alignment. // Source operands are: the address, the N vectors, the lane number, and
def int_arm_neon_vst1 : Intrinsic<[], // the alignment.
[llvm_ptr_ty, llvm_anyvector_ty, def int_arm_neon_vst2lane : Intrinsic<[],
llvm_i32_ty], [IntrReadWriteArgMem]>; [llvm_ptr_ty, llvm_anyvector_ty,
def int_arm_neon_vst2 : Intrinsic<[], LLVMMatchType<0>, llvm_i32_ty,
[llvm_ptr_ty, llvm_anyvector_ty, llvm_i32_ty], [IntrReadWriteArgMem]>;
LLVMMatchType<0>, llvm_i32_ty], def int_arm_neon_vst3lane : Intrinsic<[],
[IntrReadWriteArgMem]>; [llvm_ptr_ty, llvm_anyvector_ty,
def int_arm_neon_vst3 : Intrinsic<[], LLVMMatchType<0>, LLVMMatchType<0>,
[llvm_ptr_ty, llvm_anyvector_ty, llvm_i32_ty, llvm_i32_ty],
LLVMMatchType<0>, LLVMMatchType<0>, [IntrReadWriteArgMem]>;
llvm_i32_ty], [IntrReadWriteArgMem]>; def int_arm_neon_vst4lane : Intrinsic<[],
def int_arm_neon_vst4 : Intrinsic<[], [llvm_ptr_ty, llvm_anyvector_ty,
[llvm_ptr_ty, llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>,
LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty,
LLVMMatchType<0>, llvm_i32_ty], llvm_i32_ty], [IntrReadWriteArgMem]>;
[IntrReadWriteArgMem]>;
// Vector store N-element structure from one lane. } // end TargetPrefix
// Source operands are: the address, the N vectors, the lane number, and
// the alignment.
def int_arm_neon_vst2lane : Intrinsic<[],
[llvm_ptr_ty, llvm_anyvector_ty,
LLVMMatchType<0>, llvm_i32_ty,
llvm_i32_ty], [IntrReadWriteArgMem]>;
def int_arm_neon_vst3lane : Intrinsic<[],
[llvm_ptr_ty, llvm_anyvector_ty,
LLVMMatchType<0>, LLVMMatchType<0>,
llvm_i32_ty, llvm_i32_ty],
[IntrReadWriteArgMem]>;
def int_arm_neon_vst4lane : Intrinsic<[],
[llvm_ptr_ty, llvm_anyvector_ty,
LLVMMatchType<0>, LLVMMatchType<0>,
LLVMMatchType<0>, llvm_i32_ty,
llvm_i32_ty], [IntrReadWriteArgMem]>;
}