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- Remove SelectSEXTi128 from SPUISelDAGToDAG.cpp, evidently, this is redundant
code, according to Anton (I'm not totally convinced, but we can always resurrect patches if we need to do so.) - Start moving CellSPU's tests to prefer FileCheck. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79958 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -322,9 +322,6 @@ namespace {
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/// target-specific node if it hasn't already been changed.
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SDNode *Select(SDValue Op);
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//! Emit the instruction sequence for i128 sext
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SDNode *SelectSEXTi128(SDValue &Op, EVT OpVT);
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//! Emit the instruction sequence for i64 shl
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SDNode *SelectSHLi64(SDValue &Op, EVT OpVT);
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@ -836,10 +833,6 @@ SPUDAGToDAGISel::Select(SDValue Op) {
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}
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}
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}
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} else if (Opc == ISD::SIGN_EXTEND) {
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if (OpVT == MVT::i128) {
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return SelectSEXTi128(Op, OpVT);
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}
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} else if (Opc == ISD::SHL) {
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if (OpVT == MVT::i64) {
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return SelectSHLi64(Op, OpVT);
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@ -963,58 +956,6 @@ SPUDAGToDAGISel::Select(SDValue Op) {
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return SelectCode(Op);
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}
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/*!
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* Emit the instruction sequence for i64 -> i128 sign extend. The basic
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* algorithm is to duplicate the sign bit using rotmai to generate at
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* least one byte full of sign bits. Then propagate the "sign-byte" into
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* theleftmost words and the i64 into the rightmost words using shufb.
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*
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* @param Op The sext operand
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* @param OpVT The type to extend to
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* @return The SDNode with the entire instruction sequence
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*/
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SDNode *
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SPUDAGToDAGISel::SelectSEXTi128(SDValue &Op, EVT OpVT)
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{
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DebugLoc dl = Op.getDebugLoc();
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// Type to extend from
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SDValue Op0 = Op.getOperand(0);
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EVT Op0VT = Op0.getValueType();
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assert((OpVT == MVT::i128 && Op0VT == MVT::i64) &&
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"LowerSIGN_EXTEND: input and/or output operand have wrong size");
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// Create shuffle mask
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unsigned mask1 = 0x10101010; // byte 0 - 3 and 4 - 7
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unsigned mask2 = 0x01020304; // byte 8 - 11
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unsigned mask3 = 0x05060708; // byte 12 - 15
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SDValue shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
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CurDAG->getConstant(mask1, MVT::i32),
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CurDAG->getConstant(mask1, MVT::i32),
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CurDAG->getConstant(mask2, MVT::i32),
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CurDAG->getConstant(mask3, MVT::i32));
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SDNode *shufMaskLoad = emitBuildVector(shufMask);
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// Word wise arithmetic right shift to generate at least one byte
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// that contains sign bits.
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SDNode *PromoteScalar = SelectCode(CurDAG->getNode(SPUISD::PREFSLOT2VEC, dl,
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MVT::v2i64, Op0, Op0));
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SDNode *sraVal = SelectCode(CurDAG->getNode(ISD::SRA, dl, MVT::v2i64,
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SDValue(PromoteScalar, 0),
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CurDAG->getConstant(31, MVT::i32)));
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// Shuffle bytes - Copy the sign bits into the upper 64 bits
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// and the input value into the lower 64 bits.
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SDNode *extShuffle = SelectCode(CurDAG->getNode(SPUISD::SHUFB, dl,
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MVT::v2i64, Op0,
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SDValue(sraVal, 0),
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SDValue(shufMaskLoad, 0)));
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return SelectCode(CurDAG->getNode(ISD::BIT_CONVERT, dl, MVT::i128,
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SDValue(extShuffle, 0)));
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}
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/*!
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* Emit the instruction sequence for i64 left shifts. The basic algorithm
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* is to fill the bottom two word slots with zeros so that zeros are shifted
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@ -1,6 +1,4 @@
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; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
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; RUN: grep {lqd.*0(\$3)} %t1.s | count 1
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; RUN: grep {lqd.*16(\$3)} %t1.s | count 1
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; RUN: llvm-as -o - %s | llc -march=cellspu | FileCheck %s
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; ModuleID = 'loads.bc'
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target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
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@ -10,11 +8,13 @@ define <4 x float> @load_v4f32_1(<4 x float>* %a) nounwind readonly {
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entry:
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%tmp1 = load <4 x float>* %a
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ret <4 x float> %tmp1
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; CHECK: lqd $3, 0($3)
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}
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define <4 x float> @load_v4f32_2(<4 x float>* %a) nounwind readonly {
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entry:
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%arrayidx = getelementptr <4 x float>* %a, i32 1 ; <<4 x float>*> [#uses=1]
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%tmp1 = load <4 x float>* %arrayidx ; <<4 x float>> [#uses=1]
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%arrayidx = getelementptr <4 x float>* %a, i32 1
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%tmp1 = load <4 x float>* %arrayidx
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ret <4 x float> %tmp1
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; CHECK: lqd $3, 16($3)
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}
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