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R600/SI: mark most intrinsics as readnone v2
They read from constant register space anyway. v2: fix lit tests Signed-off-by: Christian König <christian.koenig@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178020 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Christian Konig
parent
03cd75eedb
commit
f623008122
@ -16,10 +16,10 @@ let TargetPrefix = "SI", isTarget = 1 in {
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def int_SI_packf16 : Intrinsic <[llvm_i32_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>;
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def int_SI_export : Intrinsic <[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty], []>;
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def int_SI_load_const : Intrinsic <[llvm_float_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrReadMem]>;
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def int_SI_vs_load_input : Intrinsic <[llvm_v4f32_ty], [llvm_v16i8_ty, llvm_i16_ty, llvm_i32_ty], [IntrReadMem]> ;
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def int_SI_load_const : Intrinsic <[llvm_float_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_SI_vs_load_input : Intrinsic <[llvm_v4f32_ty], [llvm_v16i8_ty, llvm_i16_ty, llvm_i32_ty], [IntrNoMem]> ;
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class Sample : Intrinsic <[llvm_v4f32_ty], [llvm_i32_ty, llvm_anyvector_ty, llvm_v32i8_ty, llvm_v16i8_ty, llvm_i32_ty], [IntrReadMem]>;
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class Sample : Intrinsic <[llvm_v4f32_ty], [llvm_i32_ty, llvm_anyvector_ty, llvm_v32i8_ty, llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_SI_sample : Sample;
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def int_SI_sampleb : Sample;
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@ -27,8 +27,8 @@ let TargetPrefix = "SI", isTarget = 1 in {
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/* Interpolation Intrinsics */
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def int_SI_fs_constant : Intrinsic <[llvm_float_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrReadMem]>;
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def int_SI_fs_interp : Intrinsic <[llvm_float_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_v2i32_ty], [IntrReadMem]>;
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def int_SI_fs_constant : Intrinsic <[llvm_float_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_SI_fs_interp : Intrinsic <[llvm_float_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_v2i32_ty], [IntrNoMem]>;
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/* Control flow Intrinsics */
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@ -14,7 +14,7 @@ main_body:
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declare void @llvm.AMDGPU.shader.type(i32)
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declare float @llvm.SI.fs.constant(i32, i32, i32) readonly
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declare float @llvm.SI.fs.constant(i32, i32, i32) readnone
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declare i32 @llvm.SI.packf16(float, float) readnone
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@ -1,71 +1,106 @@
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;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
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;CHECK: IMAGE_SAMPLE
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;CHECK-NEXT: S_WAITCNT 1904
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;CHECK-NEXT: IMAGE_SAMPLE
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;CHECK-NEXT: S_WAITCNT 1904
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;CHECK-NEXT: IMAGE_SAMPLE
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;CHECK-NEXT: S_WAITCNT 1904
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;CHECK-NEXT: IMAGE_SAMPLE
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;CHECK-NEXT: S_WAITCNT 1904
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;CHECK-NEXT: IMAGE_SAMPLE
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;CHECK-NEXT: S_WAITCNT 1904
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;CHECK-NEXT: IMAGE_SAMPLE_C
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;CHECK-NEXT: S_WAITCNT 1904
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;CHECK-NEXT: IMAGE_SAMPLE_C
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;CHECK-NEXT: S_WAITCNT 1904
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;CHECK-NEXT: IMAGE_SAMPLE_C
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;CHECK-NEXT: S_WAITCNT 1904
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;CHECK-NEXT: IMAGE_SAMPLE
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;CHECK-NEXT: S_WAITCNT 1904
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;CHECK-NEXT: IMAGE_SAMPLE
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;CHECK-NEXT: S_WAITCNT 1904
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;CHECK-NEXT: IMAGE_SAMPLE_C
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;CHECK-NEXT: S_WAITCNT 1904
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;CHECK-NEXT: IMAGE_SAMPLE_C
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;CHECK-NEXT: S_WAITCNT 1904
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;CHECK-NEXT: IMAGE_SAMPLE_C
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;CHECK-NEXT: S_WAITCNT 1904
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;CHECK-NEXT: IMAGE_SAMPLE
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;CHECK-NEXT: S_WAITCNT 1904
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;CHECK-NEXT: IMAGE_SAMPLE
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;CHECK-NEXT: S_WAITCNT 1904
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;CHECK-NEXT: IMAGE_SAMPLE
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;CHECK: IMAGE_SAMPLE
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;CHECK: IMAGE_SAMPLE
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;CHECK: IMAGE_SAMPLE
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;CHECK: IMAGE_SAMPLE
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;CHECK: IMAGE_SAMPLE_C
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;CHECK: IMAGE_SAMPLE_C
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;CHECK: IMAGE_SAMPLE_C
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;CHECK: IMAGE_SAMPLE
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;CHECK: IMAGE_SAMPLE
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;CHECK: IMAGE_SAMPLE_C
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;CHECK: IMAGE_SAMPLE_C
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;CHECK: IMAGE_SAMPLE_C
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;CHECK: IMAGE_SAMPLE
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;CHECK: IMAGE_SAMPLE
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;CHECK: IMAGE_SAMPLE
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define void @test() {
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%res1 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef,
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define void @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4) {
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%v1 = insertelement <4 x i32> undef, i32 %a1, i32 0
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%v2 = insertelement <4 x i32> undef, i32 %a1, i32 1
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%v3 = insertelement <4 x i32> undef, i32 %a1, i32 2
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%v4 = insertelement <4 x i32> undef, i32 %a1, i32 3
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%v5 = insertelement <4 x i32> undef, i32 %a2, i32 0
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%v6 = insertelement <4 x i32> undef, i32 %a2, i32 1
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%v7 = insertelement <4 x i32> undef, i32 %a2, i32 2
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%v8 = insertelement <4 x i32> undef, i32 %a2, i32 3
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%v9 = insertelement <4 x i32> undef, i32 %a3, i32 0
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%v10 = insertelement <4 x i32> undef, i32 %a3, i32 1
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%v11 = insertelement <4 x i32> undef, i32 %a3, i32 2
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%v12 = insertelement <4 x i32> undef, i32 %a3, i32 3
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%v13 = insertelement <4 x i32> undef, i32 %a4, i32 0
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%v14 = insertelement <4 x i32> undef, i32 %a4, i32 1
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%v15 = insertelement <4 x i32> undef, i32 %a4, i32 2
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%v16 = insertelement <4 x i32> undef, i32 %a4, i32 3
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%res1 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v1,
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<8 x i32> undef, <4 x i32> undef, i32 1)
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%res2 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef,
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%res2 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v2,
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<8 x i32> undef, <4 x i32> undef, i32 2)
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%res3 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef,
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%res3 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v3,
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<8 x i32> undef, <4 x i32> undef, i32 3)
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%res4 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef,
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%res4 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v4,
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<8 x i32> undef, <4 x i32> undef, i32 4)
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%res5 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef,
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%res5 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v5,
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<8 x i32> undef, <4 x i32> undef, i32 5)
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%res6 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef,
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%res6 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v6,
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<8 x i32> undef, <4 x i32> undef, i32 6)
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%res7 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef,
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%res7 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v7,
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<8 x i32> undef, <4 x i32> undef, i32 7)
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%res8 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef,
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%res8 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v8,
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<8 x i32> undef, <4 x i32> undef, i32 8)
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%res9 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef,
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%res9 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v9,
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<8 x i32> undef, <4 x i32> undef, i32 9)
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%res10 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef,
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%res10 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v10,
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<8 x i32> undef, <4 x i32> undef, i32 10)
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%res11 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef,
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%res11 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v11,
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<8 x i32> undef, <4 x i32> undef, i32 11)
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%res12 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef,
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%res12 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v12,
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<8 x i32> undef, <4 x i32> undef, i32 12)
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%res13 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef,
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%res13 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v13,
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<8 x i32> undef, <4 x i32> undef, i32 13)
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%res14 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef,
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%res14 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v14,
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<8 x i32> undef, <4 x i32> undef, i32 14)
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%res15 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef,
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%res15 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v15,
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<8 x i32> undef, <4 x i32> undef, i32 15)
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%res16 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> undef,
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%res16 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v16,
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<8 x i32> undef, <4 x i32> undef, i32 16)
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%e1 = extractelement <4 x float> %res1, i32 0
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%e2 = extractelement <4 x float> %res2, i32 0
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%e3 = extractelement <4 x float> %res3, i32 0
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%e4 = extractelement <4 x float> %res4, i32 0
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%e5 = extractelement <4 x float> %res5, i32 0
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%e6 = extractelement <4 x float> %res6, i32 0
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%e7 = extractelement <4 x float> %res7, i32 0
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%e8 = extractelement <4 x float> %res8, i32 0
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%e9 = extractelement <4 x float> %res9, i32 0
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%e10 = extractelement <4 x float> %res10, i32 0
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%e11 = extractelement <4 x float> %res11, i32 0
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%e12 = extractelement <4 x float> %res12, i32 0
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%e13 = extractelement <4 x float> %res13, i32 0
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%e14 = extractelement <4 x float> %res14, i32 0
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%e15 = extractelement <4 x float> %res15, i32 0
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%e16 = extractelement <4 x float> %res16, i32 0
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%s1 = fadd float %e1, %e2
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%s2 = fadd float %s1, %e3
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%s3 = fadd float %s2, %e4
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%s4 = fadd float %s3, %e5
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%s5 = fadd float %s4, %e6
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%s6 = fadd float %s5, %e7
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%s7 = fadd float %s6, %e8
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%s8 = fadd float %s7, %e9
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%s9 = fadd float %s8, %e10
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%s10 = fadd float %s9, %e11
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%s11 = fadd float %s10, %e12
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%s12 = fadd float %s11, %e13
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%s13 = fadd float %s12, %e14
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%s14 = fadd float %s13, %e15
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%s15 = fadd float %s14, %e16
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call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %s15, float %s15, float %s15, float %s15)
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ret void
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}
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declare <4 x float> @llvm.SI.sample.(i32, <4 x i32>, <8 x i32>, <4 x i32>, i32)
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declare <4 x float> @llvm.SI.sample.(i32, <4 x i32>, <8 x i32>, <4 x i32>, i32) readnone
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declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
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