mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-12 13:30:51 +00:00
[Hexagon] Adding encodings for JR class instructions. Updating complier usages.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223967 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu
parent
c0e334099c
commit
f6492bc6b2
@ -59,13 +59,13 @@ private:
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char HexagonCFGOptimizer::ID = 0;
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static bool IsConditionalBranch(int Opc) {
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return (Opc == Hexagon::JMP_t) || (Opc == Hexagon::JMP_f)
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|| (Opc == Hexagon::JMP_tnew_t) || (Opc == Hexagon::JMP_fnew_t);
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return (Opc == Hexagon::J2_jumpt) || (Opc == Hexagon::J2_jumpf)
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|| (Opc == Hexagon::J2_jumptnewpt) || (Opc == Hexagon::J2_jumpfnewpt);
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}
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static bool IsUnconditionalJump(int Opc) {
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return (Opc == Hexagon::JMP);
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return (Opc == Hexagon::J2_jump);
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}
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@ -75,20 +75,20 @@ HexagonCFGOptimizer::InvertAndChangeJumpTarget(MachineInstr* MI,
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const HexagonInstrInfo *QII = QTM.getSubtargetImpl()->getInstrInfo();
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int NewOpcode = 0;
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switch(MI->getOpcode()) {
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case Hexagon::JMP_t:
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NewOpcode = Hexagon::JMP_f;
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case Hexagon::J2_jumpt:
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NewOpcode = Hexagon::J2_jumpf;
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break;
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case Hexagon::JMP_f:
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NewOpcode = Hexagon::JMP_t;
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case Hexagon::J2_jumpf:
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NewOpcode = Hexagon::J2_jumpt;
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break;
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case Hexagon::JMP_tnew_t:
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NewOpcode = Hexagon::JMP_fnew_t;
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case Hexagon::J2_jumptnewpt:
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NewOpcode = Hexagon::J2_jumpfnewpt;
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break;
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case Hexagon::JMP_fnew_t:
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NewOpcode = Hexagon::JMP_tnew_t;
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case Hexagon::J2_jumpfnewpt:
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NewOpcode = Hexagon::J2_jumptnewpt;
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break;
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default:
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@ -163,8 +163,8 @@ bool HexagonCFGOptimizer::runOnMachineFunction(MachineFunction &Fn) {
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// The target of the unconditional branch must be JumpAroundTarget.
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// TODO: If not, we should not invert the unconditional branch.
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MachineBasicBlock* CondBranchTarget = nullptr;
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if ((MI->getOpcode() == Hexagon::JMP_t) ||
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(MI->getOpcode() == Hexagon::JMP_f)) {
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if ((MI->getOpcode() == Hexagon::J2_jumpt) ||
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(MI->getOpcode() == Hexagon::J2_jumpf)) {
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CondBranchTarget = MI->getOperand(1).getMBB();
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}
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@ -1122,8 +1122,8 @@ bool HexagonHardwareLoops::convertToHardwareLoop(MachineLoop *L) {
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// The loop ends with either:
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// - a conditional branch followed by an unconditional branch, or
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// - a conditional branch to the loop start.
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if (LastI->getOpcode() == Hexagon::JMP_t ||
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LastI->getOpcode() == Hexagon::JMP_f) {
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if (LastI->getOpcode() == Hexagon::J2_jumpt ||
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LastI->getOpcode() == Hexagon::J2_jumpf) {
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// Delete one and change/add an uncond. branch to out of the loop.
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MachineBasicBlock *BranchTarget = LastI->getOperand(1).getMBB();
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LastI = LastMBB->erase(LastI);
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@ -186,7 +186,7 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
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string InputType = ""; // Input is "imm" or "reg" type.
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string isMEMri = "false"; // Set to "true" for load/store with MEMri operand.
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string isFloat = "false"; // Set to "true" for the floating-point load/store.
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string isBrTaken = ""; // Set to "true"/"false" for jump instructions
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string isBrTaken = !if(isTaken, "true", "false"); // Set to "true"/"false" for jump instructions
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let PredSense = !if(isPredicated, !if(isPredicatedFalse, "false", "true"),
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"");
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@ -124,8 +124,8 @@ HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL) const{
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int BOpc = Hexagon::JMP;
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int BccOpc = Hexagon::JMP_t;
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int BOpc = Hexagon::J2_jump;
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int BccOpc = Hexagon::J2_jumpt;
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assert(TBB && "InsertBranch must not be told to insert a fallthrough");
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@ -134,7 +134,7 @@ HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
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// If we want to reverse the branch an odd number of times, we want
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// JMP_f.
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if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
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BccOpc = Hexagon::JMP_f;
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BccOpc = Hexagon::J2_jumpf;
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regPos = 1;
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}
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@ -213,7 +213,7 @@ bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
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}
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// Delete the JMP if it's equivalent to a fall-through.
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if (AllowModify && I->getOpcode() == Hexagon::JMP &&
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if (AllowModify && I->getOpcode() == Hexagon::J2_jump &&
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MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
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DEBUG(dbgs()<< "\nErasing the jump to successor block\n";);
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I->eraseFromParent();
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@ -249,7 +249,7 @@ bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
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// If there is only one terminator instruction, process it.
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if (LastInst && !SecondLastInst) {
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if (LastOpcode == Hexagon::JMP) {
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if (LastOpcode == Hexagon::J2_jump) {
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TBB = LastInst->getOperand(0).getMBB();
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return false;
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}
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@ -274,7 +274,7 @@ bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
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bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c(SecLastOpcode);
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bool SecLastOpcodeHasNot = PredOpcodeHasNot(SecLastOpcode);
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if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::JMP)) {
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if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) {
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TBB = SecondLastInst->getOperand(1).getMBB();
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if (SecLastOpcodeHasNot)
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Cond.push_back(MachineOperand::CreateImm(0));
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@ -285,7 +285,7 @@ bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
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// If the block ends with two Hexagon:JMPs, handle it. The second one is not
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// executed, so remove it.
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if (SecLastOpcode == Hexagon::JMP && LastOpcode == Hexagon::JMP) {
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if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) {
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TBB = SecondLastInst->getOperand(0).getMBB();
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I = LastInst;
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if (AllowModify)
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@ -295,7 +295,7 @@ bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
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// If the block ends with an ENDLOOP, and JMP, handle it.
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if (SecLastOpcode == Hexagon::ENDLOOP0 &&
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LastOpcode == Hexagon::JMP) {
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LastOpcode == Hexagon::J2_jump) {
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TBB = SecondLastInst->getOperand(0).getMBB();
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Cond.push_back(SecondLastInst->getOperand(0));
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FBB = LastInst->getOperand(0).getMBB();
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@ -308,9 +308,9 @@ bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
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unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
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int BOpc = Hexagon::JMP;
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int BccOpc = Hexagon::JMP_t;
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int BccOpcNot = Hexagon::JMP_f;
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int BOpc = Hexagon::J2_jump;
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int BccOpc = Hexagon::J2_jumpt;
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int BccOpcNot = Hexagon::J2_jumpf;
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MachineBasicBlock::iterator I = MBB.end();
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if (I == MBB.begin()) return 0;
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@ -1609,21 +1609,21 @@ int HexagonInstrInfo::GetDotNewPredOp(MachineInstr *MI,
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switch (MI->getOpcode()) {
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default: llvm_unreachable("Unknown .new type");
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// Condtional Jumps
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case Hexagon::JMP_t:
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case Hexagon::JMP_f:
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case Hexagon::J2_jumpt:
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case Hexagon::J2_jumpf:
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return getDotNewPredJumpOp(MI, MBPI);
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case Hexagon::JMPR_t:
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return Hexagon::JMPR_tnew_tV3;
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case Hexagon::J2_jumprt:
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return Hexagon::J2_jumptnewpt;
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case Hexagon::JMPR_f:
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return Hexagon::JMPR_fnew_tV3;
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case Hexagon::J2_jumprf:
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return Hexagon::J2_jumprfnewpt;
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case Hexagon::JMPret_t:
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return Hexagon::JMPret_tnew_tV3;
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case Hexagon::JMPrett:
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return Hexagon::J2_jumprtnewpt;
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case Hexagon::JMPret_f:
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return Hexagon::JMPret_fnew_tV3;
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case Hexagon::JMPretf:
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return Hexagon::J2_jumprfnewpt;
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// Conditional combine
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@ -1747,10 +1747,10 @@ HexagonInstrInfo::getDotNewPredJumpOp(MachineInstr *MI,
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taken = true;
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switch (MI->getOpcode()) {
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case Hexagon::JMP_t:
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return taken ? Hexagon::JMP_tnew_t : Hexagon::JMP_tnew_nt;
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case Hexagon::JMP_f:
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return taken ? Hexagon::JMP_fnew_t : Hexagon::JMP_fnew_nt;
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case Hexagon::J2_jumpt:
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return taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
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case Hexagon::J2_jumpf:
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return taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
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default:
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llvm_unreachable("Unexpected jump instruction.");
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@ -1862,16 +1862,16 @@ short HexagonInstrInfo::getNonExtOpcode (const MachineInstr *MI) const {
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}
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bool HexagonInstrInfo::PredOpcodeHasJMP_c(Opcode_t Opcode) const {
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return (Opcode == Hexagon::JMP_t) ||
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(Opcode == Hexagon::JMP_f) ||
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(Opcode == Hexagon::JMP_tnew_t) ||
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(Opcode == Hexagon::JMP_fnew_t) ||
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(Opcode == Hexagon::JMP_tnew_nt) ||
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(Opcode == Hexagon::JMP_fnew_nt);
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return (Opcode == Hexagon::J2_jumpt) ||
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(Opcode == Hexagon::J2_jumpf) ||
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(Opcode == Hexagon::J2_jumptnewpt) ||
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(Opcode == Hexagon::J2_jumpfnewpt) ||
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(Opcode == Hexagon::J2_jumpt) ||
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(Opcode == Hexagon::J2_jumpf);
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}
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bool HexagonInstrInfo::PredOpcodeHasNot(Opcode_t Opcode) const {
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return (Opcode == Hexagon::JMP_f) ||
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(Opcode == Hexagon::JMP_fnew_t) ||
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(Opcode == Hexagon::JMP_fnew_nt);
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return (Opcode == Hexagon::J2_jumpf) ||
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(Opcode == Hexagon::J2_jumpfnewpt) ||
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(Opcode == Hexagon::J2_jumpfnew);
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}
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@ -1264,22 +1264,33 @@ def VSPLICE_rrp : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
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// CR -
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// JR +
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//===----------------------------------------------------------------------===//
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def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone,
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[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
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def eh_return: SDNode<"HexagonISD::EH_RETURN", SDTNone,
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[SDNPHasChain]>;
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def eh_return: SDNode<"HexagonISD::EH_RETURN", SDTNone, [SDNPHasChain]>;
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def SDHexagonBR_JT: SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
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def HexagonBR_JT: SDNode<"HexagonISD::BR_JT", SDHexagonBR_JT, [SDNPHasChain]>;
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let InputType = "imm", isBarrier = 1, isPredicable = 1,
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Defs = [PC], isExtendable = 1, opExtendable = 0, isExtentSigned = 1,
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opExtentBits = 24, isCodeGenOnly = 0 in
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class T_JMP <dag InsDag, list<dag> JumpList = []>
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: JInst<(outs), InsDag,
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"jump $dst" , JumpList> {
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bits<24> dst;
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class CondStr<string CReg, bit True, bit New> {
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string S = "if (" # !if(True,"","!") # CReg # !if(New,".new","") # ") ";
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}
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class JumpOpcStr<string Mnemonic, bit New, bit Taken> {
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string S = Mnemonic # !if(New, !if(Taken,":t",":nt"), "");
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}
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let isBranch = 1, isBarrier = 1, Defs = [PC], hasSideEffects = 0,
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isPredicable = 1,
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isExtendable = 1, opExtendable = 0, isExtentSigned = 1,
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opExtentBits = 24, opExtentAlign = 2, InputType = "imm" in
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class T_JMP<string ExtStr>
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: JInst<(outs), (ins brtarget:$dst),
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"jump " # ExtStr # "$dst",
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[], "", J_tc_2early_SLOT23> {
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bits<24> dst;
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let IClass = 0b0101;
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let Inst{27-25} = 0b100;
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@ -1287,16 +1298,16 @@ class T_JMP <dag InsDag, list<dag> JumpList = []>
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let Inst{13-1} = dst{14-2};
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}
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let InputType = "imm", isExtendable = 1, opExtendable = 1, isExtentSigned = 1,
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Defs = [PC], isPredicated = 1, opExtentBits = 17 in
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class T_JMP_c <bit PredNot, bit isPredNew, bit isTak>:
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JInst<(outs ), (ins PredRegs:$src, brtarget:$dst),
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!if(PredNot, "if (!$src", "if ($src")#
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!if(isPredNew, ".new) ", ") ")#"jump"#
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!if(isPredNew, !if(isTak, ":t ", ":nt "), " ")#"$dst"> {
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let isBranch = 1, Defs = [PC], hasSideEffects = 0, isPredicated = 1,
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isExtendable = 1, opExtendable = 1, isExtentSigned = 1,
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opExtentBits = 17, opExtentAlign = 2, InputType = "imm" in
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class T_JMP_c<bit PredNot, bit isPredNew, bit isTak, string ExtStr>
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: JInst<(outs), (ins PredRegs:$src, brtarget:$dst),
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CondStr<"$src", !if(PredNot,0,1), isPredNew>.S #
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JumpOpcStr<"jump", isPredNew, isTak>.S # " " #
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ExtStr # "$dst",
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[], "", J_tc_2early_SLOT23>, ImmRegRel {
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let isTaken = isTak;
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let isBrTaken = !if(isPredNew, !if(isTaken, "true", "false"), "");
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let isPredicatedFalse = PredNot;
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let isPredicatedNew = isPredNew;
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bits<2> src;
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@ -1315,11 +1326,28 @@ class T_JMP_c <bit PredNot, bit isPredNew, bit isTak>:
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let Inst{7-1} = dst{8-2};
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}
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let isBarrier = 1, Defs = [PC], isPredicable = 1, InputType = "reg" in
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class T_JMPr<dag InsDag = (ins IntRegs:$dst)>
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: JRInst<(outs ), InsDag,
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"jumpr $dst" ,
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[]> {
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multiclass JMP_Pred<bit PredNot, string ExtStr> {
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def NAME : T_JMP_c<PredNot, 0, 0, ExtStr>;
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// Predicate new
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def NAME#newpt : T_JMP_c<PredNot, 1, 1, ExtStr>; // taken
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def NAME#new : T_JMP_c<PredNot, 1, 0, ExtStr>; // not taken
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}
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multiclass JMP_base<string BaseOp, string ExtStr> {
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let BaseOpcode = BaseOp in {
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def NAME : T_JMP<ExtStr>;
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defm t : JMP_Pred<0, ExtStr>;
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defm f : JMP_Pred<1, ExtStr>;
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}
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}
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// Jumps to address stored in a register, JUMPR_MISC
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// if ([[!]P[.new]]) jumpr[:t/nt] Rs
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let isBranch = 1, isIndirectBranch = 1, isBarrier = 1, Defs = [PC],
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isPredicable = 1, hasSideEffects = 0, InputType = "reg" in
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class T_JMPr
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: JRInst<(outs), (ins IntRegs:$dst),
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"jumpr $dst", [], "", J_tc_2early_SLOT2> {
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bits<5> dst;
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let IClass = 0b0101;
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@ -1327,15 +1355,15 @@ class T_JMPr<dag InsDag = (ins IntRegs:$dst)>
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let Inst{20-16} = dst;
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}
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let Defs = [PC], isPredicated = 1, InputType = "reg" in
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class T_JMPr_c <bit PredNot, bit isPredNew, bit isTak>:
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JRInst <(outs ), (ins PredRegs:$src, IntRegs:$dst),
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!if(PredNot, "if (!$src", "if ($src")#
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!if(isPredNew, ".new) ", ") ")#"jumpr"#
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!if(isPredNew, !if(isTak, ":t ", ":nt "), " ")#"$dst"> {
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let isBranch = 1, isIndirectBranch = 1, Defs = [PC], isPredicated = 1,
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hasSideEffects = 0, InputType = "reg" in
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class T_JMPr_c <bit PredNot, bit isPredNew, bit isTak>
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: JRInst <(outs), (ins PredRegs:$src, IntRegs:$dst),
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CondStr<"$src", !if(PredNot,0,1), isPredNew>.S #
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JumpOpcStr<"jumpr", isPredNew, isTak>.S # " $dst", [],
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"", J_tc_2early_SLOT2> {
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let isTaken = isTak;
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let isBrTaken = !if(isPredNew, !if(isTaken, "true", "false"), "");
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let isPredicatedFalse = PredNot;
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let isPredicatedNew = isPredNew;
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bits<2> src;
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@ -1349,37 +1377,20 @@ class T_JMPr_c <bit PredNot, bit isPredNew, bit isTak>:
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let Inst{12} = !if(isPredNew, isTak, zero);
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let Inst{11} = isPredNew;
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let Inst{9-8} = src;
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let Predicates = !if(isPredNew, [HasV3T], [HasV2T]);
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let validSubTargets = !if(isPredNew, HasV3SubT, HasV2SubT);
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}
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|
||||
multiclass JMP_Pred<bit PredNot> {
|
||||
def _#NAME : T_JMP_c<PredNot, 0, 0>;
|
||||
// Predicate new
|
||||
def _#NAME#new_t : T_JMP_c<PredNot, 1, 1>; // taken
|
||||
def _#NAME#new_nt : T_JMP_c<PredNot, 1, 0>; // not taken
|
||||
}
|
||||
|
||||
multiclass JMP_base<string BaseOp> {
|
||||
let BaseOpcode = BaseOp in {
|
||||
def NAME : T_JMP<(ins brtarget:$dst), [(br bb:$dst)]>;
|
||||
defm t : JMP_Pred<0>;
|
||||
defm f : JMP_Pred<1>;
|
||||
}
|
||||
}
|
||||
|
||||
multiclass JMPR_Pred<bit PredNot> {
|
||||
def NAME: T_JMPr_c<PredNot, 0, 0>;
|
||||
// Predicate new
|
||||
def NAME#new_tV3 : T_JMPr_c<PredNot, 1, 1>; // taken
|
||||
def NAME#new_ntV3 : T_JMPr_c<PredNot, 1, 0>; // not taken
|
||||
def NAME#newpt : T_JMPr_c<PredNot, 1, 1>; // taken
|
||||
def NAME#new : T_JMPr_c<PredNot, 1, 0>; // not taken
|
||||
}
|
||||
|
||||
multiclass JMPR_base<string BaseOp> {
|
||||
let BaseOpcode = BaseOp in {
|
||||
def NAME : T_JMPr;
|
||||
defm _t : JMPR_Pred<0>;
|
||||
defm _f : JMPR_Pred<1>;
|
||||
defm t : JMPR_Pred<0>;
|
||||
defm f : JMPR_Pred<1>;
|
||||
}
|
||||
}
|
||||
|
||||
@ -1411,36 +1422,40 @@ let Defs = VolatileV3.Regs, isCodeGenOnly = 0 in {
|
||||
def J2_callrf : JUMPR_MISC_CALLR<1, 1, (ins PredRegs:$Pu, IntRegs:$Rs)>;
|
||||
}
|
||||
|
||||
let isTerminator = 1, hasSideEffects = 0 in {
|
||||
let isBranch = 1 in
|
||||
defm JMP : JMP_base<"JMP">, PredNewRel;
|
||||
let isTerminator = 1, hasSideEffects = 0, isCodeGenOnly = 0 in {
|
||||
defm J2_jump : JMP_base<"JMP", "">, PredNewRel;
|
||||
|
||||
let isBranch = 1, isIndirectBranch = 1 in
|
||||
defm JMPR : JMPR_base<"JMPr">, PredNewRel;
|
||||
// Deal with explicit assembly
|
||||
// - never extened a jump #, always extend a jump ##
|
||||
let isAsmParserOnly = 1 in {
|
||||
defm J2_jump_ext : JMP_base<"JMP", "##">;
|
||||
defm J2_jump_noext : JMP_base<"JMP", "#">;
|
||||
}
|
||||
|
||||
let isReturn = 1, isCodeGenOnly = 1 in
|
||||
defm JMPret : JMPR_base<"JMPret">, PredNewRel;
|
||||
defm J2_jumpr : JMPR_base<"JMPr">, PredNewRel;
|
||||
|
||||
let isReturn = 1, isCodeGenOnly = 1 in
|
||||
defm JMPret : JMPR_base<"JMPret">, PredNewRel;
|
||||
}
|
||||
|
||||
def : Pat<(retflag),
|
||||
(JMPret (i32 R31))>;
|
||||
|
||||
def : Pat <(brcond (i1 PredRegs:$src1), bb:$offset),
|
||||
(JMP_t (i1 PredRegs:$src1), bb:$offset)>;
|
||||
def: Pat<(br bb:$dst),
|
||||
(J2_jump brtarget:$dst)>;
|
||||
def: Pat<(retflag),
|
||||
(JMPret (i32 R31))>;
|
||||
def: Pat<(brcond (i1 PredRegs:$src1), bb:$offset),
|
||||
(J2_jumpt PredRegs:$src1, bb:$offset)>;
|
||||
|
||||
// A return through builtin_eh_return.
|
||||
let isReturn = 1, isTerminator = 1, isBarrier = 1, hasSideEffects = 0,
|
||||
isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in
|
||||
isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in
|
||||
def EH_RETURN_JMPR : T_JMPr;
|
||||
|
||||
def : Pat<(eh_return),
|
||||
(EH_RETURN_JMPR (i32 R31))>;
|
||||
|
||||
def : Pat<(HexagonBR_JT (i32 IntRegs:$dst)),
|
||||
(JMPR (i32 IntRegs:$dst))>;
|
||||
|
||||
def : Pat<(brind (i32 IntRegs:$dst)),
|
||||
(JMPR (i32 IntRegs:$dst))>;
|
||||
def: Pat<(eh_return),
|
||||
(EH_RETURN_JMPR (i32 R31))>;
|
||||
def: Pat<(HexagonBR_JT (i32 IntRegs:$dst)),
|
||||
(J2_jumpr IntRegs:$dst)>;
|
||||
def: Pat<(brind (i32 IntRegs:$dst)),
|
||||
(J2_jumpr IntRegs:$dst)>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// JR -
|
||||
@ -2639,15 +2654,9 @@ let isCall = 1, hasSideEffects = 0,
|
||||
"call $dst", []>;
|
||||
}
|
||||
|
||||
// Call subroutine from register.
|
||||
let isCall = 1, hasSideEffects = 0,
|
||||
Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
|
||||
R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
|
||||
def CALLR : JRInst<(outs), (ins IntRegs:$dst),
|
||||
"callr $dst",
|
||||
[]>;
|
||||
}
|
||||
|
||||
// Call subroutine indirectly.
|
||||
let Defs = VolatileV3.Regs, isCodeGenOnly = 0 in
|
||||
def J2_callr : JUMPR_MISC_CALLR<0, 1>;
|
||||
|
||||
// Indirect tail-call.
|
||||
let isCodeGenOnly = 1, isCall = 1, isReturn = 1 in
|
||||
@ -2656,13 +2665,15 @@ def TCRETURNR : T_JMPr;
|
||||
// Direct tail-calls.
|
||||
let isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
|
||||
isTerminator = 1, isCodeGenOnly = 1 in {
|
||||
def TCRETURNtg : T_JMP<(ins calltarget:$dst)>;
|
||||
def TCRETURNtext : T_JMP<(ins calltarget:$dst)>;
|
||||
def TCRETURNtg : JInst<(outs), (ins calltarget:$dst), "jump $dst",
|
||||
[], "", J_tc_2early_SLOT23>;
|
||||
def TCRETURNtext : JInst<(outs), (ins calltarget:$dst), "jump $dst",
|
||||
[], "", J_tc_2early_SLOT23>;
|
||||
}
|
||||
|
||||
// Map call instruction.
|
||||
def : Pat<(call (i32 IntRegs:$dst)),
|
||||
(CALLR (i32 IntRegs:$dst))>, Requires<[HasV2TOnly]>;
|
||||
(J2_callr (i32 IntRegs:$dst))>, Requires<[HasV2TOnly]>;
|
||||
def : Pat<(call tglobaladdr:$dst),
|
||||
(CALL tglobaladdr:$dst)>, Requires<[HasV2TOnly]>;
|
||||
def : Pat<(call texternalsym:$dst),
|
||||
@ -2774,7 +2785,7 @@ def : Pat <(select (not (i1 PredRegs:$src1)), IntRegs:$src2, s12ImmPred:$src3),
|
||||
|
||||
// Map from p0 = pnot(p0); if (p0) jump => if (!p0) jump.
|
||||
def : Pat <(brcond (not (i1 PredRegs:$src1)), bb:$offset),
|
||||
(JMP_f (i1 PredRegs:$src1), bb:$offset)>;
|
||||
(J2_jumpf (i1 PredRegs:$src1), bb:$offset)>;
|
||||
|
||||
// Map from p2 = pnot(p2); p1 = and(p0, p2) => p1 = and(p0, !p2).
|
||||
def : Pat <(and (i1 PredRegs:$src1), (not (i1 PredRegs:$src2))),
|
||||
@ -2807,46 +2818,46 @@ def : Pat <(i64 (sext_inreg (i64 DoubleRegs:$src1), i8)),
|
||||
subreg_loreg))))))>;
|
||||
|
||||
// We want to prevent emitting pnot's as much as possible.
|
||||
// Map brcond with an unsupported setcc to a JMP_f.
|
||||
// Map brcond with an unsupported setcc to a J2_jumpf.
|
||||
def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
|
||||
bb:$offset),
|
||||
(JMP_f (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
|
||||
(J2_jumpf (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
|
||||
bb:$offset)>;
|
||||
|
||||
def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)),
|
||||
bb:$offset),
|
||||
(JMP_f (C2_cmpeqi (i32 IntRegs:$src1), s10ImmPred:$src2), bb:$offset)>;
|
||||
(J2_jumpf (C2_cmpeqi (i32 IntRegs:$src1), s10ImmPred:$src2), bb:$offset)>;
|
||||
|
||||
def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 -1))), bb:$offset),
|
||||
(JMP_f (i1 PredRegs:$src1), bb:$offset)>;
|
||||
(J2_jumpf (i1 PredRegs:$src1), bb:$offset)>;
|
||||
|
||||
def : Pat <(brcond (i1 (setne (i1 PredRegs:$src1), (i1 0))), bb:$offset),
|
||||
(JMP_t (i1 PredRegs:$src1), bb:$offset)>;
|
||||
(J2_jumpt (i1 PredRegs:$src1), bb:$offset)>;
|
||||
|
||||
// cmp.lt(Rs, Imm) -> !cmp.ge(Rs, Imm) -> !cmp.gt(Rs, Imm-1)
|
||||
def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)),
|
||||
bb:$offset),
|
||||
(JMP_f (C2_cmpgti (i32 IntRegs:$src1),
|
||||
(J2_jumpf (C2_cmpgti (i32 IntRegs:$src1),
|
||||
(DEC_CONST_SIGNED s8ImmPred:$src2)), bb:$offset)>;
|
||||
|
||||
// cmp.lt(r0, r1) -> cmp.gt(r1, r0)
|
||||
def : Pat <(brcond (i1 (setlt (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
|
||||
bb:$offset),
|
||||
(JMP_t (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)), bb:$offset)>;
|
||||
(J2_jumpt (C2_cmpgt (i32 IntRegs:$src2), (i32 IntRegs:$src1)), bb:$offset)>;
|
||||
|
||||
def : Pat <(brcond (i1 (setuge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
|
||||
bb:$offset),
|
||||
(JMP_f (C2_cmpgtup (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)),
|
||||
(J2_jumpf (C2_cmpgtup (i64 DoubleRegs:$src2), (i64 DoubleRegs:$src1)),
|
||||
bb:$offset)>;
|
||||
|
||||
def : Pat <(brcond (i1 (setule (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
|
||||
bb:$offset),
|
||||
(JMP_f (C2_cmpgtu (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
|
||||
(J2_jumpf (C2_cmpgtu (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
|
||||
bb:$offset)>;
|
||||
|
||||
def : Pat <(brcond (i1 (setule (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
|
||||
bb:$offset),
|
||||
(JMP_f (C2_cmpgtup (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
|
||||
(J2_jumpf (C2_cmpgtup (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2)),
|
||||
bb:$offset)>;
|
||||
|
||||
// Map from a 64-bit select to an emulated 64-bit mux.
|
||||
|
||||
@ -2204,7 +2204,7 @@ def CMPbEQri_V4 : MInst<(outs PredRegs:$dst),
|
||||
|
||||
def : Pat <(brcond (i1 (setne (and (i32 IntRegs:$src1), 255), u8ImmPred:$src2)),
|
||||
bb:$offset),
|
||||
(JMP_f (CMPbEQri_V4 (i32 IntRegs:$src1), u8ImmPred:$src2),
|
||||
(J2_jumpf (CMPbEQri_V4 (i32 IntRegs:$src1), u8ImmPred:$src2),
|
||||
bb:$offset)>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
|
||||
@ -473,15 +473,6 @@ def : Pat <(f64 (bitconvert (i64 DoubleRegs:$src))),
|
||||
(f64 (A2_tfrp DoubleRegs:$src))>,
|
||||
Requires<[HasV5T]>;
|
||||
|
||||
// Floating point fused multiply-add.
|
||||
def FMADD_dp : ALU64_acc<(outs DoubleRegs:$dst),
|
||||
(ins DoubleRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3),
|
||||
"$dst += dfmpy($src2, $src3)",
|
||||
[(set (f64 DoubleRegs:$dst),
|
||||
(fma DoubleRegs:$src2, DoubleRegs:$src3, DoubleRegs:$src1))],
|
||||
"$src1 = $dst">,
|
||||
Requires<[HasV5T]>;
|
||||
|
||||
def FMADD_sp : ALU64_acc<(outs IntRegs:$dst),
|
||||
(ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
|
||||
"$dst += sfmpy($src2, $src3)",
|
||||
@ -492,15 +483,6 @@ def FMADD_sp : ALU64_acc<(outs IntRegs:$dst),
|
||||
|
||||
|
||||
// Floating point max/min.
|
||||
let AddedComplexity = 100 in
|
||||
def FMAX_dp : ALU64_rr<(outs DoubleRegs:$dst),
|
||||
(ins DoubleRegs:$src1, DoubleRegs:$src2),
|
||||
"$dst = dfmax($src1, $src2)",
|
||||
[(set DoubleRegs:$dst, (f64 (select (i1 (setolt DoubleRegs:$src2,
|
||||
DoubleRegs:$src1)),
|
||||
DoubleRegs:$src1,
|
||||
DoubleRegs:$src2)))]>,
|
||||
Requires<[HasV5T]>;
|
||||
|
||||
let AddedComplexity = 100 in
|
||||
def FMAX_sp : ALU64_rr<(outs IntRegs:$dst),
|
||||
@ -512,16 +494,6 @@ def FMAX_sp : ALU64_rr<(outs IntRegs:$dst),
|
||||
IntRegs:$src2)))]>,
|
||||
Requires<[HasV5T]>;
|
||||
|
||||
let AddedComplexity = 100 in
|
||||
def FMIN_dp : ALU64_rr<(outs DoubleRegs:$dst),
|
||||
(ins DoubleRegs:$src1, DoubleRegs:$src2),
|
||||
"$dst = dfmin($src1, $src2)",
|
||||
[(set DoubleRegs:$dst, (f64 (select (i1 (setogt DoubleRegs:$src2,
|
||||
DoubleRegs:$src1)),
|
||||
DoubleRegs:$src1,
|
||||
DoubleRegs:$src2)))]>,
|
||||
Requires<[HasV5T]>;
|
||||
|
||||
let AddedComplexity = 100 in
|
||||
def FMIN_sp : ALU64_rr<(outs IntRegs:$dst),
|
||||
(ins IntRegs:$src1, IntRegs:$src2),
|
||||
|
||||
@ -412,12 +412,12 @@ bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
|
||||
DEBUG(dbgs() << "Instr: "; MI->dump(); dbgs() << "\n");
|
||||
|
||||
if (!foundJump &&
|
||||
(MI->getOpcode() == Hexagon::JMP_t ||
|
||||
MI->getOpcode() == Hexagon::JMP_f ||
|
||||
MI->getOpcode() == Hexagon::JMP_tnew_t ||
|
||||
MI->getOpcode() == Hexagon::JMP_tnew_nt ||
|
||||
MI->getOpcode() == Hexagon::JMP_fnew_t ||
|
||||
MI->getOpcode() == Hexagon::JMP_fnew_nt)) {
|
||||
(MI->getOpcode() == Hexagon::J2_jumpt ||
|
||||
MI->getOpcode() == Hexagon::J2_jumpf ||
|
||||
MI->getOpcode() == Hexagon::J2_jumptnewpt ||
|
||||
MI->getOpcode() == Hexagon::J2_jumptnew ||
|
||||
MI->getOpcode() == Hexagon::J2_jumpfnewpt ||
|
||||
MI->getOpcode() == Hexagon::J2_jumpfnew)) {
|
||||
// This is where you would insert your compare and
|
||||
// instr that feeds compare
|
||||
jmpPos = MII;
|
||||
@ -453,9 +453,9 @@ bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
|
||||
|
||||
jmpTarget = MI->getOperand(1).getMBB();
|
||||
foundJump = true;
|
||||
if (MI->getOpcode() == Hexagon::JMP_f ||
|
||||
MI->getOpcode() == Hexagon::JMP_fnew_t ||
|
||||
MI->getOpcode() == Hexagon::JMP_fnew_nt) {
|
||||
if (MI->getOpcode() == Hexagon::J2_jumpf ||
|
||||
MI->getOpcode() == Hexagon::J2_jumpfnewpt ||
|
||||
MI->getOpcode() == Hexagon::J2_jumpfnew) {
|
||||
invertPredicate = true;
|
||||
}
|
||||
continue;
|
||||
|
||||
@ -264,7 +264,7 @@ bool HexagonPacketizer::runOnMachineFunction(MachineFunction &Fn) {
|
||||
|
||||
|
||||
static bool IsIndirectCall(MachineInstr* MI) {
|
||||
return ((MI->getOpcode() == Hexagon::CALLR) ||
|
||||
return ((MI->getOpcode() == Hexagon::J2_callr) ||
|
||||
(MI->getOpcode() == Hexagon::CALLRv3));
|
||||
}
|
||||
|
||||
@ -366,7 +366,7 @@ static bool IsRegDependence(const SDep::Kind DepType) {
|
||||
}
|
||||
|
||||
static bool IsDirectJump(MachineInstr* MI) {
|
||||
return (MI->getOpcode() == Hexagon::JMP);
|
||||
return (MI->getOpcode() == Hexagon::J2_jump);
|
||||
}
|
||||
|
||||
static bool IsSchedBarrier(MachineInstr* MI) {
|
||||
|
||||
@ -1,6 +1,26 @@
|
||||
# RUN: llvm-mc -triple hexagon -disassemble < %s | FileCheck %s
|
||||
|
||||
0x00 0xc0 0xb5 0x50
|
||||
# CHECK: callr r21
|
||||
0x00 0xc1 0x15 0x51
|
||||
# CHECK: if (p1) callr r21
|
||||
0x00 0xc3 0x35 0x51
|
||||
# CHECK: if (!p3) callr r21
|
||||
0x00 0xc0 0x95 0x52
|
||||
# CHECK: jumpr r21
|
||||
0x00 0xc1 0x55 0x53
|
||||
# CHECK: if (p1) jumpr r21
|
||||
0x03 0x40 0x45 0x85 0x00 0xcb 0x55 0x53
|
||||
# CHECK: p3 = r5
|
||||
# CHECK-NEXT: if (p3.new) jumpr:nt r21
|
||||
0x03 0x40 0x45 0x85 0x00 0xdb 0x55 0x53
|
||||
# CHECK: p3 = r5
|
||||
# CHECK-NEXT: if (p3.new) jumpr:t r21
|
||||
0x00 0xc3 0x75 0x53
|
||||
# CHECK: if (!p3) jumpr r21
|
||||
0x03 0x40 0x45 0x85 0x00 0xcb 0x75 0x53
|
||||
# CHECK: p3 = r5
|
||||
# CHECK-NEXT: if (!p3.new) jumpr:nt r21
|
||||
0x03 0x40 0x45 0x85 0x00 0xdb 0x75 0x53
|
||||
# CHECK: p3 = r5
|
||||
# CHECK-NEXT: if (!p3.new) jumpr:t r21
|
||||
|
||||
Loading…
Reference in New Issue
Block a user