mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-12 16:29:31 +00:00
add missing point at the end of sentences
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145943 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sebastian Pop
parent
88c09143b6
commit
f6f77e90a1
@ -42,35 +42,35 @@ private:
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const int (*DFAStateInputTable)[2];
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const unsigned *DFAStateEntryTable;
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// CachedTable is a map from <FromState, Input> to ToState
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// CachedTable is a map from <FromState, Input> to ToState.
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DenseMap<UnsignPair, unsigned> CachedTable;
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// ReadTable - Read the DFA transition table and update CachedTable
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// ReadTable - Read the DFA transition table and update CachedTable.
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void ReadTable(unsigned int state);
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public:
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DFAPacketizer(const InstrItineraryData* I, const int (*SIT)[2],
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const unsigned* SET);
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// Reset the current state to make all resources available
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// Reset the current state to make all resources available.
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void clearResources() {
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CurrentState = 0;
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}
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// canReserveResources - Check if the resources occupied by a MCInstrDesc
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// are available in the current state
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// are available in the current state.
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bool canReserveResources(const llvm::MCInstrDesc* MID);
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// reserveResources - Reserve the resources occupied by a MCInstrDesc and
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// change the current state to reflect that change
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// change the current state to reflect that change.
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void reserveResources(const llvm::MCInstrDesc* MID);
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// canReserveResources - Check if the resources occupied by a machine
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// instruction are available in the current state
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// instruction are available in the current state.
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bool canReserveResources(llvm::MachineInstr* MI);
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// reserveResources - Reserve the resources occupied by a machine
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// instruction and change the current state to reflect that change
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// instruction and change the current state to reflect that change.
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void reserveResources(llvm::MachineInstr* MI);
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};
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}
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@ -35,7 +35,7 @@ DFAPacketizer::DFAPacketizer(const InstrItineraryData *I, const int (*SIT)[2],
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//
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// ReadTable - Read the DFA transition table and update CachedTable
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// ReadTable - Read the DFA transition table and update CachedTable.
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//
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// Format of the transition tables:
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// DFAStateInputTable[][2] = pairs of <Input, Transition> for all valid
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@ -47,7 +47,7 @@ void DFAPacketizer::ReadTable(unsigned int state) {
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unsigned ThisState = DFAStateEntryTable[state];
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unsigned NextStateInTable = DFAStateEntryTable[state+1];
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// Early exit in case CachedTable has already contains this
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// state's transitions
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// state's transitions.
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if (CachedTable.count(UnsignPair(state,
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DFAStateInputTable[ThisState][0])))
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return;
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@ -59,7 +59,7 @@ void DFAPacketizer::ReadTable(unsigned int state) {
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// canReserveResources - Check if the resources occupied by a MCInstrDesc
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// are available in the current state
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// are available in the current state.
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bool DFAPacketizer::canReserveResources(const llvm::MCInstrDesc* MID) {
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unsigned InsnClass = MID->getSchedClass();
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const llvm::InstrStage* IS = InstrItins->beginStage(InsnClass);
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@ -71,7 +71,7 @@ bool DFAPacketizer::canReserveResources(const llvm::MCInstrDesc* MID) {
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// reserveResources - Reserve the resources occupied by a MCInstrDesc and
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// change the current state to reflect that change
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// change the current state to reflect that change.
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void DFAPacketizer::reserveResources(const llvm::MCInstrDesc* MID) {
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unsigned InsnClass = MID->getSchedClass();
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const llvm::InstrStage* IS = InstrItins->beginStage(InsnClass);
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@ -84,14 +84,14 @@ void DFAPacketizer::reserveResources(const llvm::MCInstrDesc* MID) {
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// canReserveResources - Check if the resources occupied by a machine
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// instruction are available in the current state
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// instruction are available in the current state.
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bool DFAPacketizer::canReserveResources(llvm::MachineInstr* MI) {
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const llvm::MCInstrDesc& MID = MI->getDesc();
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return canReserveResources(&MID);
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}
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// reserveResources - Reserve the resources occupied by a machine
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// instruction and change the current state to reflect that change
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// instruction and change the current state to reflect that change.
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void DFAPacketizer::reserveResources(llvm::MachineInstr* MI) {
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const llvm::MCInstrDesc& MID = MI->getDesc();
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reserveResources(&MID);
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@ -29,19 +29,19 @@ using namespace llvm;
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// State represents the usage of machine resources if the packet contains
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// a set of instruction classes.
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//
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// Specifically, currentState is a set of bit-masks
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// Specifically, currentState is a set of bit-masks.
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// The nth bit in a bit-mask indicates whether the nth resource is being used
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// by this state. The set of bit-masks in a state represent the different
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// possible outcomes of transitioning to this state.
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// For example: Consider a two resource architecture: Resource L and Resource M
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// with three instruction classes: L, M, and L_or_M
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// For example: consider a two resource architecture: resource L and resource M
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// with three instruction classes: L, M, and L_or_M.
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// From the initial state (currentState = 0x00), if we add instruction class
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// L_or_M we will transition to a state with currentState = [0x01, 0x10]. This
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// represents the possible resource states that can result from adding a L_or_M
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// instruction
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//
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// Another way of thinking about this transition is we are mapping a NDFA with
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// two states [0x01] and [0x10] into a DFA with a single state [0x01, 0x10]
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// two states [0x01] and [0x10] into a DFA with a single state [0x01, 0x10].
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//
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//
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namespace {
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@ -57,15 +57,15 @@ class State {
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//
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// canAddInsnClass - Returns true if an instruction of type InsnClass is a
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// valid transition from this state i.e., can an instruction of type InsnClass
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// be added to the packet represented by this state
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// valid transition from this state, i.e., can an instruction of type InsnClass
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// be added to the packet represented by this state.
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//
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// PossibleStates is the set of valid resource states that ensue from valid
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// transitions
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// transitions.
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//
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bool canAddInsnClass(unsigned InsnClass, std::set<unsigned>& PossibleStates);
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};
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} // End anonymous namespace
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} // End anonymous namespace.
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namespace {
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@ -79,39 +79,39 @@ struct Transition {
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Transition(State* from_, unsigned input_, State* to_);
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};
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} // End anonymous namespace
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} // End anonymous namespace.
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//
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// Comparators to keep set of states sorted
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// Comparators to keep set of states sorted.
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//
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namespace {
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struct ltState {
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bool operator()(const State* s1, const State* s2) const;
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};
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} // End anonymous namespace
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} // End anonymous namespace.
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//
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// class DFA: deterministic finite automaton for processor resource tracking
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// class DFA: deterministic finite automaton for processor resource tracking.
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//
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namespace {
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class DFA {
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public:
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DFA();
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// Set of states. Need to keep this sorted to emit the transition table
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// Set of states. Need to keep this sorted to emit the transition table.
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std::set<State*, ltState> states;
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// Map from a state to the list of transitions with that state as source
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// Map from a state to the list of transitions with that state as source.
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std::map<State*, SmallVector<Transition*, 16>, ltState> stateTransitions;
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State* currentState;
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// Highest valued Input seen
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// Highest valued Input seen.
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unsigned LargestInput;
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//
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// Modify the DFA
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// Modify the DFA.
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//
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void initialize();
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void addState(State*);
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@ -119,22 +119,22 @@ public:
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//
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// getTransition - Return the state when a transition is made from
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// State From with Input I. If a transition is not found, return NULL
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// State From with Input I. If a transition is not found, return NULL.
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//
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State* getTransition(State*, unsigned);
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//
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// isValidTransition: Predicate that checks if there is a valid transition
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// from state From on input InsnClass
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// from state From on input InsnClass.
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//
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bool isValidTransition(State* From, unsigned InsnClass);
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//
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// writeTable: Print out a table representing the DFA
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// writeTable: Print out a table representing the DFA.
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//
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void writeTableAndAPI(raw_ostream &OS, const std::string& ClassName);
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};
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} // End anonymous namespace
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} // End anonymous namespace.
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//
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@ -166,15 +166,15 @@ bool ltState::operator()(const State* s1, const State* s2) const {
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//
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// canAddInsnClass - Returns true if an instruction of type InsnClass is a
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// valid transition from this state i.e., can an instruction of type InsnClass
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// be added to the packet represented by this state
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// be added to the packet represented by this state.
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//
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// PossibleStates is the set of valid resource states that ensue from valid
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// transitions
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// transitions.
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//
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bool State::canAddInsnClass(unsigned InsnClass,
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std::set<unsigned>& PossibleStates) {
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//
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// Iterate over all resource states in currentState
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// Iterate over all resource states in currentState.
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//
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bool AddedState = false;
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@ -183,8 +183,8 @@ bool State::canAddInsnClass(unsigned InsnClass,
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unsigned thisState = *SI;
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//
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// Iterate over all possible resources used in InsnClass
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// For ex: for InsnClass = 0x11, all resources = {0x01, 0x10}
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// Iterate over all possible resources used in InsnClass.
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// For ex: for InsnClass = 0x11, all resources = {0x01, 0x10}.
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//
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DenseSet<unsigned> VisitedResourceStates;
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@ -192,18 +192,18 @@ bool State::canAddInsnClass(unsigned InsnClass,
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if ((0x1 << j) & InsnClass) {
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//
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// For each possible resource used in InsnClass, generate the
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// resource state if that resource was used
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// resource state if that resource was used.
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//
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unsigned ResultingResourceState = thisState | (0x1 << j);
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//
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// Check if the resulting resource state can be accommodated in this
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// packet
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// We compute ResultingResourceState OR thisState
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// packet.
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// We compute ResultingResourceState OR thisState.
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// If the result of the OR is different than thisState, it implies
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// that there is at least one resource that can be used to schedule
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// InsnClass in the current packet
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// InsnClass in the current packet.
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// Insert ResultingResourceState into PossibleStates only if we haven't
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// processed ResultingResourceState before
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// processed ResultingResourceState before.
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//
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if ((ResultingResourceState != thisState) &&
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(VisitedResourceStates.count(ResultingResourceState) == 0)) {
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@ -231,18 +231,18 @@ void DFA::addState(State* S) {
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void DFA::addTransition(Transition* T) {
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// Update LargestInput
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// Update LargestInput.
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if (T->input > LargestInput)
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LargestInput = T->input;
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// Add the new transition
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// Add the new transition.
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stateTransitions[T->from].push_back(T);
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}
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//
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// getTransition - Return the state when a transition is made from
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// State From with Input I. If a transition is not found, return NULL
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// State From with Input I. If a transition is not found, return NULL.
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//
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State* DFA::getTransition(State* From, unsigned I) {
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// Do we have a transition from state From?
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@ -275,26 +275,26 @@ DFAGen::DFAGen(RecordKeeper& R):
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//
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// writeTableAndAPI - Print out a table representing the DFA and the
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// associated API to create a DFA packetizer
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// associated API to create a DFA packetizer.
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//
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// Format:
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// DFAStateInputTable[][2] = pairs of <Input, Transition> for all valid
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// transitions
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// transitions.
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// DFAStateEntryTable[i] = Index of the first entry in DFAStateInputTable for
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// the ith state
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// the ith state.
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//
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//
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void DFA::writeTableAndAPI(raw_ostream &OS, const std::string& TargetName) {
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std::set<State*, ltState>::iterator SI = states.begin();
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// This table provides a map to the beginning of the transitions for State s
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// in DFAStateInputTable i.e.,
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// in DFAStateInputTable.
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std::vector<int> StateEntry(states.size());
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OS << "namespace llvm {\n\n";
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OS << "const int " << TargetName << "DFAStateInputTable[][2] = {\n";
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// Tracks the total valid transitions encountered so far. It is used
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// to construct the StateEntry table
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// to construct the StateEntry table.
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int ValidTransitions = 0;
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for (unsigned i = 0; i < states.size(); ++i, ++SI) {
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StateEntry[i] = ValidTransitions;
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@ -309,8 +309,8 @@ void DFA::writeTableAndAPI(raw_ostream &OS, const std::string& TargetName) {
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++ValidTransitions;
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}
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/* If there are no valid transitions from this stage, we need a sentinel
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transition */
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// If there are no valid transitions from this stage, we need a sentinel
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// transition.
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if (ValidTransitions == StateEntry[i])
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OS << "{-1, -1},";
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@ -320,7 +320,7 @@ void DFA::writeTableAndAPI(raw_ostream &OS, const std::string& TargetName) {
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OS << "const unsigned int " << TargetName << "DFAStateEntryTable[] = {\n";
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// Multiply i by 2 since each entry in DFAStateInputTable is a set of
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// two numbers
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// two numbers.
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for (unsigned i = 0; i < states.size(); ++i)
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OS << StateEntry[i] << ", ";
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@ -329,7 +329,7 @@ void DFA::writeTableAndAPI(raw_ostream &OS, const std::string& TargetName) {
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//
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// Emit DFA Packetizer tables if the target is a VLIW machine
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// Emit DFA Packetizer tables if the target is a VLIW machine.
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//
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std::string SubTargetClassName = TargetName + "GenSubtargetInfo";
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OS << "\n" << "#include \"llvm/CodeGen/DFAPacketizer.h\"\n";
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@ -350,11 +350,11 @@ void DFAGen::collectAllInsnClasses(const std::string &Name,
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Record *ItinData,
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unsigned &NStages,
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raw_ostream &OS) {
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// Collect processor itineraries
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// Collect processor itineraries.
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std::vector<Record*> ProcItinList =
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Records.getAllDerivedDefinitions("ProcessorItineraries");
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Records.getAllDerivedDefinitions("ProcessorItineraries");
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// If just no itinerary then don't bother
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// If just no itinerary then don't bother.
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if (ProcItinList.size() < 2)
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return;
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std::map<std::string, unsigned> NameToBitsMap;
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@ -364,7 +364,7 @@ void DFAGen::collectAllInsnClasses(const std::string &Name,
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Record *Proc = ProcItinList[i];
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std::vector<Record*> FUs = Proc->getValueAsListOfDefs("FU");
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// Convert macros to bits for each stage
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// Convert macros to bits for each stage.
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for (unsigned i = 0, N = FUs.size(); i < N; ++i)
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NameToBitsMap[FUs[i]->getName()] = (unsigned) (1U << i);
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}
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@ -372,22 +372,22 @@ void DFAGen::collectAllInsnClasses(const std::string &Name,
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const std::vector<Record*> &StageList =
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ItinData->getValueAsListOfDefs("Stages");
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// The number of stages
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// The number of stages.
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NStages = StageList.size();
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// For each unit
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// For each unit.
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unsigned UnitBitValue = 0;
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// Compute the bitwise or of each unit used in this stage
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// Compute the bitwise or of each unit used in this stage.
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for (unsigned i = 0; i < NStages; ++i) {
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const Record *Stage = StageList[i];
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// Get unit list
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// Get unit list.
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const std::vector<Record*> &UnitList =
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Stage->getValueAsListOfDefs("Units");
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for (unsigned j = 0, M = UnitList.size(); j < M; ++j) {
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// Conduct bitwise or
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// Conduct bitwise or.
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std::string UnitName = UnitList[j]->getName();
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assert(NameToBitsMap.count(UnitName));
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UnitBitValue |= NameToBitsMap[UnitName];
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@ -400,38 +400,38 @@ void DFAGen::collectAllInsnClasses(const std::string &Name,
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//
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// Run the worklist algorithm to generate the DFA
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// Run the worklist algorithm to generate the DFA.
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//
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void DFAGen::run(raw_ostream &OS) {
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EmitSourceFileHeader("Target DFA Packetizer Tables", OS);
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// Collect processor iteraries
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// Collect processor iteraries.
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std::vector<Record*> ProcItinList =
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Records.getAllDerivedDefinitions("ProcessorItineraries");
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//
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// Collect the instruction classes
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// Collect the instruction classes.
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//
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for (unsigned i = 0, N = ProcItinList.size(); i < N; i++) {
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Record *Proc = ProcItinList[i];
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// Get processor itinerary name
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// Get processor itinerary name.
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const std::string &Name = Proc->getName();
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// Skip default
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// Skip default.
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if (Name == "NoItineraries")
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continue;
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// Sanity check for at least one instruction itinerary class
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// Sanity check for at least one instruction itinerary class.
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unsigned NItinClasses =
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Records.getAllDerivedDefinitions("InstrItinClass").size();
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if (NItinClasses == 0)
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return;
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// Get itinerary data list
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// Get itinerary data list.
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std::vector<Record*> ItinDataList = Proc->getValueAsListOfDefs("IID");
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// Collect instruction classes for all itinerary data
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// Collect instruction classes for all itinerary data.
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for (unsigned j = 0, M = ItinDataList.size(); j < M; j++) {
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Record *ItinData = ItinDataList[j];
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unsigned NStages;
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@ -441,7 +441,7 @@ void DFAGen::run(raw_ostream &OS) {
|
||||
|
||||
|
||||
//
|
||||
// Run a worklist algorithm to generate the DFA
|
||||
// Run a worklist algorithm to generate the DFA.
|
||||
//
|
||||
DFA D;
|
||||
State* Initial = new State;
|
||||
@ -454,7 +454,7 @@ void DFAGen::run(raw_ostream &OS) {
|
||||
WorkList.push_back(Initial);
|
||||
|
||||
//
|
||||
// Worklist algorithm to create a DFA for processor resource tracking
|
||||
// Worklist algorithm to create a DFA for processor resource tracking.
|
||||
// C = {set of InsnClasses}
|
||||
// Begin with initial node in worklist. Initial node does not have
|
||||
// any consumed resources,
|
||||
@ -479,14 +479,14 @@ void DFAGen::run(raw_ostream &OS) {
|
||||
std::set<unsigned> NewStateResources;
|
||||
//
|
||||
// If we haven't already created a transition for this input
|
||||
// and the state can accommodate this InsnClass, create a transition
|
||||
// and the state can accommodate this InsnClass, create a transition.
|
||||
//
|
||||
if (!D.getTransition(current, InsnClass) &&
|
||||
current->canAddInsnClass(InsnClass, NewStateResources)) {
|
||||
State* NewState = NULL;
|
||||
|
||||
//
|
||||
// If we have seen this state before, then do not create a new state
|
||||
// If we have seen this state before, then do not create a new state.
|
||||
//
|
||||
//
|
||||
std::map<std::set<unsigned>, State*>::iterator VI;
|
||||
@ -507,6 +507,6 @@ void DFAGen::run(raw_ostream &OS) {
|
||||
}
|
||||
}
|
||||
|
||||
// Print out the table
|
||||
// Print out the table.
|
||||
D.writeTableAndAPI(OS, TargetName);
|
||||
}
|
||||
|
||||
@ -25,14 +25,14 @@
|
||||
namespace llvm {
|
||||
//
|
||||
// class DFAGen: class that generates and prints out the DFA for resource
|
||||
// tracking
|
||||
// tracking.
|
||||
//
|
||||
class DFAGen : public TableGenBackend {
|
||||
private:
|
||||
std::string TargetName;
|
||||
//
|
||||
// allInsnClasses is the set of all possible resources consumed by an
|
||||
// InstrStage
|
||||
// InstrStage.
|
||||
//
|
||||
DenseSet<unsigned> allInsnClasses;
|
||||
RecordKeeper &Records;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user