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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 18:29:45 +00:00
Remove the old TRI::ResolveRegAllocHint() and getRawAllocationOrder() hooks.
These functions have been replaced by TRI::getRegAllocationHints() which provides the same capabilities. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169192 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
parent
46f6fe7a45
commit
f714156460
@ -614,19 +614,6 @@ public:
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virtual const int *getRegClassPressureSets(
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const TargetRegisterClass *RC) const = 0;
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/// getRawAllocationOrder - Returns the register allocation order for a
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/// specified register class with a target-dependent hint. The returned list
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/// may contain reserved registers that cannot be allocated.
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///
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/// Register allocators need only call this function to resolve
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/// target-dependent hints, but it should work without hinting as well.
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virtual ArrayRef<MCPhysReg>
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getRawAllocationOrder(const TargetRegisterClass *RC,
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unsigned HintType, unsigned HintReg,
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const MachineFunction &MF) const {
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return RC->getRawAllocationOrder(MF);
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}
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/// Get a list of 'hint' registers that the register allocator should try
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/// first when allocating a physical register for the virtual register
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/// VirtReg. These registers are effectively moved to the front of the
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@ -647,15 +634,6 @@ public:
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const MachineFunction &MF,
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const VirtRegMap *VRM = 0) const;
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/// ResolveRegAllocHint - Resolves the specified register allocation hint
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/// to a physical register. Returns the physical register if it is successful.
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virtual unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
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const MachineFunction &MF) const {
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if (Type == 0 && Reg && isPhysicalRegister(Reg))
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return Reg;
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return 0;
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}
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/// avoidWriteAfterWrite - Return true if the register allocator should avoid
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/// writing a register from RC in two consecutive instructions.
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/// This can avoid pipeline stalls on certain architectures.
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@ -232,156 +232,6 @@ ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg,
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}
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}
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/// getRawAllocationOrder - Returns the register allocation order for a
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/// specified register class with a target-dependent hint.
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ArrayRef<uint16_t>
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ARMBaseRegisterInfo::getRawAllocationOrder(const TargetRegisterClass *RC,
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unsigned HintType, unsigned HintReg,
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const MachineFunction &MF) const {
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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// Alternative register allocation orders when favoring even / odd registers
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// of register pairs.
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// No FP, R9 is available.
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static const uint16_t GPREven1[] = {
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ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
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ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
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ARM::R9, ARM::R11
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};
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static const uint16_t GPROdd1[] = {
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ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
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ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
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ARM::R8, ARM::R10
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};
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// FP is R7, R9 is available.
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static const uint16_t GPREven2[] = {
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ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10,
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ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
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ARM::R9, ARM::R11
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};
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static const uint16_t GPROdd2[] = {
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ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11,
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ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
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ARM::R8, ARM::R10
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};
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// FP is R11, R9 is available.
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static const uint16_t GPREven3[] = {
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ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
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ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
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ARM::R9
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};
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static const uint16_t GPROdd3[] = {
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ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
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ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
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ARM::R8
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};
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// No FP, R9 is not available.
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static const uint16_t GPREven4[] = {
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ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10,
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ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
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ARM::R11
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};
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static const uint16_t GPROdd4[] = {
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ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11,
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ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
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ARM::R10
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};
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// FP is R7, R9 is not available.
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static const uint16_t GPREven5[] = {
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ARM::R0, ARM::R2, ARM::R4, ARM::R10,
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ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
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ARM::R11
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};
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static const uint16_t GPROdd5[] = {
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ARM::R1, ARM::R3, ARM::R5, ARM::R11,
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ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
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ARM::R10
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};
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// FP is R11, R9 is not available.
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static const uint16_t GPREven6[] = {
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ARM::R0, ARM::R2, ARM::R4, ARM::R6,
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ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
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};
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static const uint16_t GPROdd6[] = {
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ARM::R1, ARM::R3, ARM::R5, ARM::R7,
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ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
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};
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// We only support even/odd hints for GPR and rGPR.
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if (RC != &ARM::GPRRegClass && RC != &ARM::rGPRRegClass)
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return RC->getRawAllocationOrder(MF);
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if (HintType == ARMRI::RegPairEven) {
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if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
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// It's no longer possible to fulfill this hint. Return the default
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// allocation order.
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return RC->getRawAllocationOrder(MF);
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if (!TFI->hasFP(MF)) {
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if (!STI.isR9Reserved())
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return makeArrayRef(GPREven1);
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else
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return makeArrayRef(GPREven4);
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} else if (FramePtr == ARM::R7) {
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if (!STI.isR9Reserved())
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return makeArrayRef(GPREven2);
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else
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return makeArrayRef(GPREven5);
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} else { // FramePtr == ARM::R11
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if (!STI.isR9Reserved())
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return makeArrayRef(GPREven3);
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else
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return makeArrayRef(GPREven6);
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}
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} else if (HintType == ARMRI::RegPairOdd) {
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if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
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// It's no longer possible to fulfill this hint. Return the default
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// allocation order.
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return RC->getRawAllocationOrder(MF);
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if (!TFI->hasFP(MF)) {
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if (!STI.isR9Reserved())
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return makeArrayRef(GPROdd1);
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else
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return makeArrayRef(GPROdd4);
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} else if (FramePtr == ARM::R7) {
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if (!STI.isR9Reserved())
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return makeArrayRef(GPROdd2);
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else
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return makeArrayRef(GPROdd5);
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} else { // FramePtr == ARM::R11
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if (!STI.isR9Reserved())
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return makeArrayRef(GPROdd3);
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else
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return makeArrayRef(GPROdd6);
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}
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}
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return RC->getRawAllocationOrder(MF);
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}
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/// ResolveRegAllocHint - Resolves the specified register allocation hint
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/// to a physical register. Returns the physical register if it is successful.
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unsigned
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ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
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const MachineFunction &MF) const {
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if (Reg == 0 || !isPhysicalRegister(Reg))
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return 0;
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if (Type == 0)
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return Reg;
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else if (Type == (unsigned)ARMRI::RegPairOdd)
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// Odd register.
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return getRegisterPairOdd(Reg, MF);
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else if (Type == (unsigned)ARMRI::RegPairEven)
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// Even register.
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return getRegisterPairEven(Reg, MF);
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return 0;
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}
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void
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ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
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MachineFunction &MF) const {
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@ -523,114 +373,6 @@ unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
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llvm_unreachable("What is the exception handler register");
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}
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unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
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const MachineFunction &MF) const {
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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switch (Reg) {
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default: break;
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// Return 0 if either register of the pair is a special register.
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// So no R12, etc.
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case ARM::R1: return ARM::R0;
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case ARM::R3: return ARM::R2;
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case ARM::R5: return ARM::R4;
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case ARM::R7:
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return (MRI.isReserved(ARM::R7) || MRI.isReserved(ARM::R6))
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? 0 : ARM::R6;
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case ARM::R9: return MRI.isReserved(ARM::R9) ? 0 :ARM::R8;
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case ARM::R11: return MRI.isReserved(ARM::R11) ? 0 : ARM::R10;
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case ARM::S1: return ARM::S0;
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case ARM::S3: return ARM::S2;
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case ARM::S5: return ARM::S4;
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case ARM::S7: return ARM::S6;
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case ARM::S9: return ARM::S8;
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case ARM::S11: return ARM::S10;
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case ARM::S13: return ARM::S12;
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case ARM::S15: return ARM::S14;
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case ARM::S17: return ARM::S16;
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case ARM::S19: return ARM::S18;
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case ARM::S21: return ARM::S20;
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case ARM::S23: return ARM::S22;
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case ARM::S25: return ARM::S24;
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case ARM::S27: return ARM::S26;
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case ARM::S29: return ARM::S28;
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case ARM::S31: return ARM::S30;
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case ARM::D1: return ARM::D0;
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case ARM::D3: return ARM::D2;
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case ARM::D5: return ARM::D4;
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case ARM::D7: return ARM::D6;
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case ARM::D9: return ARM::D8;
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case ARM::D11: return ARM::D10;
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case ARM::D13: return ARM::D12;
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case ARM::D15: return ARM::D14;
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case ARM::D17: return ARM::D16;
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case ARM::D19: return ARM::D18;
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case ARM::D21: return ARM::D20;
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case ARM::D23: return ARM::D22;
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case ARM::D25: return ARM::D24;
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case ARM::D27: return ARM::D26;
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case ARM::D29: return ARM::D28;
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case ARM::D31: return ARM::D30;
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}
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return 0;
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}
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unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
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const MachineFunction &MF) const {
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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switch (Reg) {
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default: break;
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// Return 0 if either register of the pair is a special register.
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// So no R12, etc.
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case ARM::R0: return ARM::R1;
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case ARM::R2: return ARM::R3;
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case ARM::R4: return ARM::R5;
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case ARM::R6:
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return (MRI.isReserved(ARM::R7) || MRI.isReserved(ARM::R6))
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? 0 : ARM::R7;
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case ARM::R8: return MRI.isReserved(ARM::R9) ? 0 :ARM::R9;
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case ARM::R10: return MRI.isReserved(ARM::R11) ? 0 : ARM::R11;
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case ARM::S0: return ARM::S1;
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case ARM::S2: return ARM::S3;
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case ARM::S4: return ARM::S5;
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case ARM::S6: return ARM::S7;
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case ARM::S8: return ARM::S9;
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case ARM::S10: return ARM::S11;
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case ARM::S12: return ARM::S13;
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case ARM::S14: return ARM::S15;
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case ARM::S16: return ARM::S17;
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case ARM::S18: return ARM::S19;
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case ARM::S20: return ARM::S21;
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case ARM::S22: return ARM::S23;
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case ARM::S24: return ARM::S25;
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case ARM::S26: return ARM::S27;
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case ARM::S28: return ARM::S29;
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case ARM::S30: return ARM::S31;
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case ARM::D0: return ARM::D1;
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case ARM::D2: return ARM::D3;
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case ARM::D4: return ARM::D5;
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case ARM::D6: return ARM::D7;
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case ARM::D8: return ARM::D9;
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case ARM::D10: return ARM::D11;
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case ARM::D12: return ARM::D13;
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case ARM::D14: return ARM::D15;
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case ARM::D16: return ARM::D17;
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case ARM::D18: return ARM::D19;
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case ARM::D20: return ARM::D21;
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case ARM::D22: return ARM::D23;
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case ARM::D24: return ARM::D25;
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case ARM::D26: return ARM::D27;
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case ARM::D28: return ARM::D29;
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case ARM::D30: return ARM::D31;
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}
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return 0;
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}
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/// emitLoadConstPool - Emits a load from constpool to materialize the
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/// specified immediate.
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void ARMBaseRegisterInfo::
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@ -111,19 +111,12 @@ public:
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unsigned getRegPressureLimit(const TargetRegisterClass *RC,
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MachineFunction &MF) const;
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ArrayRef<uint16_t> getRawAllocationOrder(const TargetRegisterClass *RC,
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unsigned HintType, unsigned HintReg,
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const MachineFunction &MF) const;
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void getRegAllocationHints(unsigned VirtReg,
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ArrayRef<MCPhysReg> Order,
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SmallVectorImpl<MCPhysReg> &Hints,
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const MachineFunction &MF,
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const VirtRegMap *VRM) const;
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unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
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const MachineFunction &MF) const;
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void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
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MachineFunction &MF) const;
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@ -181,11 +174,6 @@ public:
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virtual void eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, RegScavenger *RS = NULL) const;
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private:
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unsigned getRegisterPairEven(unsigned Reg, const MachineFunction &MF) const;
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unsigned getRegisterPairOdd(unsigned Reg, const MachineFunction &MF) const;
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};
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} // end namespace llvm
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