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Revert "[FastISel][AArch64] Fold bit test and branch into TBZ and TBNZ."
Reverting it until I have time to investigate a regression. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218035 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1860,7 +1860,7 @@ static AArch64CC::CondCode getCompareCC(CmpInst::Predicate Pred) {
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/// \brief Check if the comparison against zero and the following branch can be
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/// folded into a single instruction (CBZ or CBNZ).
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static bool canFoldZeroCheckIntoBranch(const CmpInst *CI) {
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static bool canFoldZeroIntoBranch(const CmpInst *CI) {
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CmpInst::Predicate Predicate = CI->getPredicate();
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if ((Predicate != CmpInst::ICMP_EQ) && (Predicate != CmpInst::ICMP_NE))
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return false;
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@ -1918,7 +1918,7 @@ bool AArch64FastISel::selectBranch(const Instruction *I) {
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}
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// Try to optimize comparisons against zero.
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if (canFoldZeroCheckIntoBranch(CI)) {
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if (canFoldZeroIntoBranch(CI)) {
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const Value *LHS = CI->getOperand(0);
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const Value *RHS = CI->getOperand(1);
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@ -1927,33 +1927,12 @@ bool AArch64FastISel::selectBranch(const Instruction *I) {
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if (C->isNullValue())
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std::swap(LHS, RHS);
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int TestBit = -1;
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if (const auto *AI = dyn_cast<BinaryOperator>(LHS))
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if (AI->getOpcode() == Instruction::And) {
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const Value *AndLHS = AI->getOperand(0);
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const Value *AndRHS = AI->getOperand(1);
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if (const auto *C = dyn_cast<ConstantInt>(AndLHS))
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if (C->getValue().isPowerOf2())
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std::swap(AndLHS, AndRHS);
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if (const auto *C = dyn_cast<ConstantInt>(AndRHS))
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if (C->getValue().isPowerOf2()) {
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TestBit = C->getValue().logBase2();
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LHS = AndLHS;
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}
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}
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static const unsigned OpcTable[2][2][2] = {
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{ {AArch64::CBZW, AArch64::CBZX },
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{AArch64::CBNZW, AArch64::CBNZX} },
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{ {AArch64::TBZW, AArch64::TBZX },
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{AArch64::TBNZW, AArch64::TBNZX} }
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static const unsigned OpcTable[2][2] = {
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{AArch64::CBZW, AArch64::CBZX }, {AArch64::CBNZW, AArch64::CBNZX}
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};
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bool IsBitTest = TestBit != -1;
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bool IsCmpNE = Predicate == CmpInst::ICMP_NE;
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bool Is64Bit = LHS->getType()->isIntegerTy(64);
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unsigned Opc = OpcTable[IsBitTest][IsCmpNE][Is64Bit];
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unsigned Opc = OpcTable[IsCmpNE][Is64Bit];
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unsigned SrcReg = getRegForValue(LHS);
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if (!SrcReg)
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@ -1961,12 +1940,9 @@ bool AArch64FastISel::selectBranch(const Instruction *I) {
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bool SrcIsKill = hasTrivialKill(LHS);
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// Emit the combined compare and branch instruction.
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MachineInstrBuilder MIB =
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
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.addReg(SrcReg, getKillRegState(SrcIsKill));
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if (IsBitTest)
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MIB.addImm(TestBit);
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MIB.addMBB(TBB);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
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.addReg(SrcReg, getKillRegState(SrcIsKill))
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.addMBB(TBB);
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// Obtain the branch weight and add the TrueBB to the successor list.
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uint32_t BranchWeight = 0;
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@ -1,50 +0,0 @@
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; RUN: llc -fast-isel -fast-isel-abort -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs -mtriple=aarch64-apple-darwin < %s | FileCheck %s
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define i32 @icmp_eq_i8(i8 zeroext %a) {
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; CHECK-LABEL: icmp_eq_i8
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; CHECK: tbz w0, #0, {{LBB.+_2}}
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%1 = and i8 %a, 1
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%2 = icmp eq i8 %1, 0
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br i1 %2, label %bb1, label %bb2
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bb2:
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ret i32 1
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bb1:
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ret i32 0
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}
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define i32 @icmp_eq_i16(i16 zeroext %a) {
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; CHECK-LABEL: icmp_eq_i16
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; CHECK: tbz w0, #1, {{LBB.+_2}}
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%1 = and i16 %a, 2
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%2 = icmp eq i16 %1, 0
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br i1 %2, label %bb1, label %bb2
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bb2:
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ret i32 1
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bb1:
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ret i32 0
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}
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define i32 @icmp_eq_i32(i32 %a) {
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; CHECK-LABEL: icmp_eq_i32
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; CHECK: tbz w0, #2, {{LBB.+_2}}
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%1 = and i32 %a, 4
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%2 = icmp eq i32 %1, 0
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br i1 %2, label %bb1, label %bb2
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bb2:
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ret i32 1
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bb1:
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ret i32 0
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}
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define i32 @icmp_eq_i64(i64 %a) {
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; CHECK-LABEL: icmp_eq_i64
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; CHECK: tbz x0, #3, {{LBB.+_2}}
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%1 = and i64 %a, 8
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%2 = icmp eq i64 %1, 0
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br i1 %2, label %bb1, label %bb2
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bb2:
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ret i32 1
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bb1:
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ret i32 0
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}
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