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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-19 04:29:21 +00:00
implement load effective address similar to the alpha backend
remove lea_addri and the now unused memri addressing mode git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31592 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -78,33 +78,6 @@ namespace {
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void printAddrMode1(const MachineInstr *MI, int opNum);
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void printAddrMode2(const MachineInstr *MI, int opNum);
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void printAddrMode5(const MachineInstr *MI, int opNum);
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void printMemRegImm(const MachineInstr *MI, int opNum,
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const char *Modifier = NULL) {
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const MachineOperand &MO1 = MI->getOperand(opNum);
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const MachineOperand &MO2 = MI->getOperand(opNum + 1);
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assert(MO1.isImmediate());
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bool arith = false;
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if (Modifier != NULL) {
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assert(strcmp(Modifier, "arith") == 0);
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arith = true;
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}
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if (MO2.isConstantPoolIndex()) {
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printOperand(MI, opNum + 1);
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} else if (MO2.isRegister()) {
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if(!arith)
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O << '[';
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printOperand(MI, opNum + 1);
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O << ", ";
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printOperand(MI, opNum);
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if(!arith)
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O << ']';
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} else {
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assert(0 && "Invalid Operand Type");
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}
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}
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void printOperand(const MachineInstr *MI, int opNum);
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void printMemOperand(const MachineInstr *MI, int opNum,
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const char *Modifier = 0);
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@ -751,8 +751,6 @@ public:
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SDNode *Select(SDOperand Op);
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virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
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bool SelectAddrRegImm(SDOperand Op, SDOperand N, SDOperand &Offset,
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SDOperand &Base);
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bool SelectAddrMode1(SDOperand Op, SDOperand N, SDOperand &Arg,
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SDOperand &Shift, SDOperand &ShiftType);
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bool SelectAddrMode2(SDOperand Op, SDOperand N, SDOperand &Arg,
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@ -895,37 +893,6 @@ bool ARMDAGToDAGISel::SelectAddrMode5(SDOperand Op,
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return true;
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}
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//register plus/minus 12 bit offset
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bool ARMDAGToDAGISel::SelectAddrRegImm(SDOperand Op,
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SDOperand N, SDOperand &Offset,
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SDOperand &Base) {
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N)) {
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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}
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if (N.getOpcode() == ISD::ADD) {
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short imm = 0;
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if (isInt12Immediate(N.getOperand(1), imm)) {
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Offset = CurDAG->getTargetConstant(imm, MVT::i32);
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if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
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Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType());
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} else {
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Base = N.getOperand(0);
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}
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return true; // [r+i]
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}
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}
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
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Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType());
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}
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else
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Base = N;
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return true; //any address fits in a register
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}
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SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
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SDNode *N = Op.Val;
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@ -933,8 +900,18 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
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default:
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return SelectCode(Op);
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break;
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case ISD::FrameIndex: {
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int FI = cast<FrameIndexSDNode>(N)->getIndex();
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SDOperand Ops[] = {CurDAG->getTargetFrameIndex(FI, MVT::i32),
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CurDAG->getTargetConstant(0, MVT::i32),
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CurDAG->getTargetConstant(0, MVT::i32),
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CurDAG->getTargetConstant(ARMShift::LSL, MVT::i32)};
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return CurDAG->SelectNodeTo(N, ARM::ADD, MVT::i32, Ops,
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sizeof(Ops)/sizeof(SDOperand));
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break;
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}
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}
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return NULL;
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}
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} // end anonymous namespace
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@ -28,11 +28,6 @@ def op_addr_mode5 : Operand<iPTR> {
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let MIOperandInfo = (ops ptr_rc, i32imm);
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}
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def memri : Operand<iPTR> {
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let PrintMethod = "printMemRegImm";
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let MIOperandInfo = (ops i32imm, ptr_rc);
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}
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// Define ARM specific addressing mode.
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//Addressing Mode 1: data processing operands
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def addr_mode1 : ComplexPattern<iPTR, 3, "SelectAddrMode1", [imm, sra, shl, srl],
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@ -44,11 +39,6 @@ def addr_mode2 : ComplexPattern<iPTR, 2, "SelectAddrMode2", [], []>;
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//Addressing Mode 5: VFP load/store
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def addr_mode5 : ComplexPattern<iPTR, 2, "SelectAddrMode5", [], []>;
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//register plus/minus 12 bit offset
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def iaddr : ComplexPattern<iPTR, 2, "SelectAddrRegImm", [frameindex], []>;
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//register plus scaled register
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//def raddr : ComplexPattern<iPTR, 2, "SelectAddrRegReg", [], []>;
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//===----------------------------------------------------------------------===//
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// Instruction Class Templates
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//===----------------------------------------------------------------------===//
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@ -203,13 +193,6 @@ def MOV : InstARM<(ops IntRegs:$dst, op_addr_mode1:$src),
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def ADD : Addr1BinOp<"add", add>;
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def ADCS : Addr1BinOp<"adcs", adde>;
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def ADDS : Addr1BinOp<"adds", addc>;
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// "LEA" forms of add
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def lea_addri : InstARM<(ops IntRegs:$dst, memri:$addr),
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"add $dst, ${addr:arith}",
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[(set IntRegs:$dst, iaddr:$addr)]>;
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def SUB : Addr1BinOp<"sub", sub>;
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def SBCS : Addr1BinOp<"sbcs", sube>;
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def SUBS : Addr1BinOp<"subs", subc>;
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@ -129,11 +129,11 @@ ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
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MachineFunction &MF = *MBB.getParent();
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assert (MI.getOpcode() == ARM::LDR ||
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MI.getOpcode() == ARM::STR ||
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MI.getOpcode() == ARM::lea_addri);
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MI.getOpcode() == ARM::STR ||
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MI.getOpcode() == ARM::ADD);
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unsigned FrameIdx = MI.getOpcode() == ARM::lea_addri ? 2 : 1;
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unsigned OffIdx = MI.getOpcode() == ARM::lea_addri ? 1 : 2;
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unsigned FrameIdx = 1;
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unsigned OffIdx = 2;
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int FrameIndex = MI.getOperand(FrameIdx).getFrameIndex();
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