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implement load effective address similar to the alpha backend

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remove lea_addri and the now unused memri addressing mode


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31592 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola 2006-11-09 13:58:55 +00:00
parent cfa0c251bd
commit f819a4999a
4 changed files with 15 additions and 82 deletions
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27
lib/Target/ARM/ARMAsmPrinter.cpp
View File

@ -78,33 +78,6 @@ namespace {
void printAddrMode1(const MachineInstr *MI, int opNum);
void printAddrMode2(const MachineInstr *MI, int opNum);
void printAddrMode5(const MachineInstr *MI, int opNum);
void printMemRegImm(const MachineInstr *MI, int opNum,
const char *Modifier = NULL) {
const MachineOperand &MO1 = MI->getOperand(opNum);
const MachineOperand &MO2 = MI->getOperand(opNum + 1);
assert(MO1.isImmediate());
bool arith = false;
if (Modifier != NULL) {
assert(strcmp(Modifier, "arith") == 0);
arith = true;
}
if (MO2.isConstantPoolIndex()) {
printOperand(MI, opNum + 1);
} else if (MO2.isRegister()) {
if(!arith)
O << '[';
printOperand(MI, opNum + 1);
O << ", ";
printOperand(MI, opNum);
if(!arith)
O << ']';
} else {
assert(0 && "Invalid Operand Type");
}
}
void printOperand(const MachineInstr *MI, int opNum);
void printMemOperand(const MachineInstr *MI, int opNum,
const char *Modifier = 0);

45
lib/Target/ARM/ARMISelDAGToDAG.cpp
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@ -751,8 +751,6 @@ public:
SDNode *Select(SDOperand Op);
virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
bool SelectAddrRegImm(SDOperand Op, SDOperand N, SDOperand &Offset,
SDOperand &Base);
bool SelectAddrMode1(SDOperand Op, SDOperand N, SDOperand &Arg,
SDOperand &Shift, SDOperand &ShiftType);
bool SelectAddrMode2(SDOperand Op, SDOperand N, SDOperand &Arg,
@ -895,37 +893,6 @@ bool ARMDAGToDAGISel::SelectAddrMode5(SDOperand Op,
return true;
}
//register plus/minus 12 bit offset
bool ARMDAGToDAGISel::SelectAddrRegImm(SDOperand Op,
SDOperand N, SDOperand &Offset,
SDOperand &Base) {
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N)) {
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
Offset = CurDAG->getTargetConstant(0, MVT::i32);
return true;
}
if (N.getOpcode() == ISD::ADD) {
short imm = 0;
if (isInt12Immediate(N.getOperand(1), imm)) {
Offset = CurDAG->getTargetConstant(imm, MVT::i32);
if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType());
} else {
Base = N.getOperand(0);
}
return true; // [r+i]
}
}
Offset = CurDAG->getTargetConstant(0, MVT::i32);
if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType());
}
else
Base = N;
return true; //any address fits in a register
}
SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
SDNode *N = Op.Val;
@ -933,8 +900,18 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
default:
return SelectCode(Op);
break;
case ISD::FrameIndex: {
int FI = cast<FrameIndexSDNode>(N)->getIndex();
SDOperand Ops[] = {CurDAG->getTargetFrameIndex(FI, MVT::i32),
CurDAG->getTargetConstant(0, MVT::i32),
CurDAG->getTargetConstant(0, MVT::i32),
CurDAG->getTargetConstant(ARMShift::LSL, MVT::i32)};
return CurDAG->SelectNodeTo(N, ARM::ADD, MVT::i32, Ops,
sizeof(Ops)/sizeof(SDOperand));
break;
}
}
return NULL;
}
} // end anonymous namespace

17
lib/Target/ARM/ARMInstrInfo.td
View File

@ -28,11 +28,6 @@ def op_addr_mode5 : Operand<iPTR> {
let MIOperandInfo = (ops ptr_rc, i32imm);
}
def memri : Operand<iPTR> {
let PrintMethod = "printMemRegImm";
let MIOperandInfo = (ops i32imm, ptr_rc);
}
// Define ARM specific addressing mode.
//Addressing Mode 1: data processing operands
def addr_mode1 : ComplexPattern<iPTR, 3, "SelectAddrMode1", [imm, sra, shl, srl],
@ -44,11 +39,6 @@ def addr_mode2 : ComplexPattern<iPTR, 2, "SelectAddrMode2", [], []>;
//Addressing Mode 5: VFP load/store
def addr_mode5 : ComplexPattern<iPTR, 2, "SelectAddrMode5", [], []>;
//register plus/minus 12 bit offset
def iaddr : ComplexPattern<iPTR, 2, "SelectAddrRegImm", [frameindex], []>;
//register plus scaled register
//def raddr : ComplexPattern<iPTR, 2, "SelectAddrRegReg", [], []>;
//===----------------------------------------------------------------------===//
// Instruction Class Templates
//===----------------------------------------------------------------------===//
@ -203,13 +193,6 @@ def MOV : InstARM<(ops IntRegs:$dst, op_addr_mode1:$src),
def ADD : Addr1BinOp<"add", add>;
def ADCS : Addr1BinOp<"adcs", adde>;
def ADDS : Addr1BinOp<"adds", addc>;
// "LEA" forms of add
def lea_addri : InstARM<(ops IntRegs:$dst, memri:$addr),
"add $dst, ${addr:arith}",
[(set IntRegs:$dst, iaddr:$addr)]>;
def SUB : Addr1BinOp<"sub", sub>;
def SBCS : Addr1BinOp<"sbcs", sube>;
def SUBS : Addr1BinOp<"subs", subc>;

8
lib/Target/ARM/ARMRegisterInfo.cpp
View File

@ -129,11 +129,11 @@ ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
MachineFunction &MF = *MBB.getParent();
assert (MI.getOpcode() == ARM::LDR ||
MI.getOpcode() == ARM::STR ||
MI.getOpcode() == ARM::lea_addri);
MI.getOpcode() == ARM::STR ||
MI.getOpcode() == ARM::ADD);
unsigned FrameIdx = MI.getOpcode() == ARM::lea_addri ? 2 : 1;
unsigned OffIdx = MI.getOpcode() == ARM::lea_addri ? 1 : 2;
unsigned FrameIdx = 1;
unsigned OffIdx = 2;
int FrameIndex = MI.getOperand(FrameIdx).getFrameIndex();