6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-15 04:30:12 +00:00
Code Issues Projects Releases Wiki Activity

Fix a bug in sdisel switch lowering code. When it updates the phi nodes in switch successor blocks, it can introduce multiple phi operands of the same value from different blocks (and may not be on the predecessor list).

Browse Source 
This can be seen on CodeGen/Generic/2006-09-06-SwitchLowering.ll. But it's not known to cause any real regression (but I have added an assertion for it now).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82214 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2009-09-18 08:16:04 +00:00
parent 1134dc5cc0
commit f8a56255a5
2 changed files with 19 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
include/llvm/CodeGen/MachineBasicBlock.h
View File

@ -149,6 +149,10 @@ public:
return (unsigned)Predecessors.size();
}
bool pred_empty() const { return Predecessors.empty(); }
bool isPred(MachineBasicBlock *MBB) const {
return std::find(pred_begin(), pred_end(), MBB) != pred_end();
}
succ_iterator succ_begin() { return Successors.begin(); }
const_succ_iterator succ_begin() const { return Successors.begin(); }
succ_iterator succ_end() { return Successors.end(); }
@ -165,6 +169,9 @@ public:
return (unsigned)Successors.size();
}
bool succ_empty() const { return Successors.empty(); }
bool isSucc(MachineBasicBlock *MBB) const {
return std::find(succ_begin(), succ_end(), MBB) != succ_end();
}
// LiveIn management methods.

17
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -982,6 +982,7 @@ SelectionDAGISel::FinishBasicBlock() {
// If we generated any switch lowering information, build and codegen any
// additional DAGs necessary.
SmallSet<unsigned, 4> Processed;
for (unsigned i = 0, e = SDL->SwitchCases.size(); i != e; ++i) {
// Set the current basic block to the mbb we wish to insert the code into
BB = SDL->SwitchCases[i].ThisBB;
@ -1004,12 +1005,18 @@ SelectionDAGISel::FinishBasicBlock() {
for (unsigned pn = 0; ; ++pn) {
assert(pn != SDL->PHINodesToUpdate.size() &&
"Didn't find PHI entry!");
if (SDL->PHINodesToUpdate[pn].first == Phi) {
Phi->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pn].
second, false));
Phi->addOperand(MachineOperand::CreateMBB(SDL->SwitchCases[i].ThisBB));
if (SDL->PHINodesToUpdate[pn].first != Phi)
continue;
if (!Processed.insert(pn))
// Already processed, done. We can't have the value from more than
// one edges.
break;
}
Phi->addOperand(MachineOperand::CreateReg(SDL->PHINodesToUpdate[pn].
second, false));
assert(BB->isPred(SDL->SwitchCases[i].ThisBB) &&
"phi value cannot come from a bb that is not a predecessor!");
Phi->addOperand(MachineOperand::CreateMBB(SDL->SwitchCases[i].ThisBB));
break;
}
}