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https://github.com/c64scene-ar/llvm-6502.git
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Add rawfrm flags
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4841 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -78,6 +78,10 @@ static bool isImmediate(const MachineOperand &MO) {
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MO.getType() == MachineOperand::MO_UnextendedImmed;
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}
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static bool isPCRelativeDisp(const MachineOperand &MO) {
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return MO.getType() == MachineOperand::MO_PCRelativeDisp;
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}
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static bool isScale(const MachineOperand &MO) {
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return isImmediate(MO) &&
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(MO.getImmedValue() == 1 || MO.getImmedValue() == 2 ||
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@ -105,6 +109,9 @@ static void printOp(std::ostream &O, const MachineOperand &MO,
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case MachineOperand::MO_UnextendedImmed:
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O << (int)MO.getImmedValue();
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return;
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case MachineOperand::MO_PCRelativeDisp:
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O << "< " << MO.getVRegValue()->getName() << ">";
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return;
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default:
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O << "<unknown op ty>"; return;
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}
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@ -305,13 +312,25 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
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break;
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case X86II::RawFrm:
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toHex(O, getBaseOpcodeFor(Opcode));
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// The accepted forms of Raw instructions are:
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// 1. nop - No operand required
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// 2. jmp foo - PC relative displacement operand
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//
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assert(MI->getNumOperands() == 0 ||
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(MI->getNumOperands() == 1 && isPCRelativeDisp(MI->getOperand(0))) &&
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"Illegal raw instruction!");
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toHex(O, getBaseOpcodeFor(Opcode)) << " ";
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if (MI->getNumOperands() == 1) {
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Value *V = MI->getOperand(0).getVRegValue();
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emitConstant(O, 0, 4);
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}
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O << "\n\t\t\t\t";
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O << getName(MI->getOpCode()) << " ";
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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if (i) O << ", ";
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printOp(O, MI->getOperand(i), RI);
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if (MI->getNumOperands() == 1) {
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printOp(O, MI->getOperand(0), RI);
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}
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O << "\n";
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return;
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@ -78,6 +78,10 @@ static bool isImmediate(const MachineOperand &MO) {
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MO.getType() == MachineOperand::MO_UnextendedImmed;
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}
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static bool isPCRelativeDisp(const MachineOperand &MO) {
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return MO.getType() == MachineOperand::MO_PCRelativeDisp;
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}
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static bool isScale(const MachineOperand &MO) {
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return isImmediate(MO) &&
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(MO.getImmedValue() == 1 || MO.getImmedValue() == 2 ||
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@ -105,6 +109,9 @@ static void printOp(std::ostream &O, const MachineOperand &MO,
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case MachineOperand::MO_UnextendedImmed:
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O << (int)MO.getImmedValue();
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return;
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case MachineOperand::MO_PCRelativeDisp:
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O << "< " << MO.getVRegValue()->getName() << ">";
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return;
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default:
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O << "<unknown op ty>"; return;
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}
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@ -305,13 +312,25 @@ void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
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break;
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case X86II::RawFrm:
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toHex(O, getBaseOpcodeFor(Opcode));
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// The accepted forms of Raw instructions are:
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// 1. nop - No operand required
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// 2. jmp foo - PC relative displacement operand
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//
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assert(MI->getNumOperands() == 0 ||
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(MI->getNumOperands() == 1 && isPCRelativeDisp(MI->getOperand(0))) &&
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"Illegal raw instruction!");
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toHex(O, getBaseOpcodeFor(Opcode)) << " ";
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if (MI->getNumOperands() == 1) {
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Value *V = MI->getOperand(0).getVRegValue();
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emitConstant(O, 0, 4);
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}
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O << "\n\t\t\t\t";
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O << getName(MI->getOpCode()) << " ";
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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if (i) O << ", ";
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printOp(O, MI->getOperand(i), RI);
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if (MI->getNumOperands() == 1) {
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printOp(O, MI->getOperand(0), RI);
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}
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O << "\n";
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return;
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@ -36,9 +36,9 @@ I(NOOP , "nop", 0x90, 0, X86II::RawFrm | X86II::Void)
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// Flow control instructions
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I(RET , "ret", 0xCB, M_RET_FLAG, X86II::RawFrm | X86II::Void) // ret
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I(JMP , "jmp", 0xE9, M_BRANCH_FLAG, X86II::Void) // jmp foo
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I(JNE , "jne", 0x85, M_BRANCH_FLAG, X86II::TB | X86II::Void)
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I(JE , "je", 0x84, M_BRANCH_FLAG, X86II::TB | X86II::Void)
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I(JMP , "jmp", 0xE9, M_BRANCH_FLAG, X86II::RawFrm | X86II::Void) // jmp foo
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I(JNE , "jne", 0x85, M_BRANCH_FLAG, X86II::RawFrm | X86II::TB | X86II::Void)
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I(JE , "je", 0x84, M_BRANCH_FLAG, X86II::RawFrm | X86II::TB | X86II::Void)
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I(CALLpcrel32 , "call", 0xE8, M_BRANCH_FLAG, X86II::Void)
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// Misc instructions
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