Shave another 27K off libllvmgcc.dylib with visibility hidden

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28973 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/MachineFunction.cpp

@@ -27,6 +27,7 @@
 #include "llvm/Instructions.h"
 #include "llvm/Support/LeakDetector.h"
 #include "llvm/Support/GraphWriter.h"
+#include "llvm/Support/Visibility.h"
 #include "llvm/Config/config.h"
 #include <fstream>
 #include <iostream>
@@ -39,7 +40,7 @@ static AnnotationID MF_AID(
 
 
 namespace {
-  struct Printer : public MachineFunctionPass {
+  struct VISIBILITY_HIDDEN Printer : public MachineFunctionPass {
     std::ostream *OS;
     const std::string Banner;
 
@@ -69,7 +70,7 @@ FunctionPass *llvm::createMachineFunctionPrinterPass(std::ostream *OS,
 }
 
 namespace {
-  struct Deleter : public MachineFunctionPass {
+  struct VISIBILITY_HIDDEN Deleter : public MachineFunctionPass {
     const char *getPassName() const { return "Machine Code Deleter"; }
 
     bool runOnMachineFunction(MachineFunction &MF) {

lib/CodeGen/PrologEpilogInserter.cpp

@@ -24,10 +24,11 @@
 #include "llvm/Target/MRegisterInfo.h"
 #include "llvm/Target/TargetFrameInfo.h"
 #include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/Support/Visibility.h"
 using namespace llvm;
 
 namespace {
-  struct PEI : public MachineFunctionPass {
+  struct VISIBILITY_HIDDEN PEI : public MachineFunctionPass {
     const char *getPassName() const {
       return "Prolog/Epilog Insertion & Frame Finalization";
     }

lib/CodeGen/RegAllocLinearScan.cpp

@@ -26,6 +26,7 @@
 #include "llvm/ADT/Statistic.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/Support/Debug.h"
+#include "llvm/Support/Visibility.h"
 #include <algorithm>
 #include <cmath>
 #include <iostream>
@@ -43,7 +44,7 @@ namespace {
   static unsigned numIterations = 0;
   static unsigned numIntervals = 0;
 
-  struct RA : public MachineFunctionPass {
+  struct VISIBILITY_HIDDEN RA : public MachineFunctionPass {
     typedef std::pair<LiveInterval*, LiveInterval::iterator> IntervalPtr;
     typedef std::vector<IntervalPtr> IntervalPtrs;
   private:

lib/CodeGen/RegAllocSimple.cpp

@@ -23,6 +23,7 @@
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Support/Debug.h"
+#include "llvm/Support/Visibility.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/ADT/STLExtras.h"
 #include <iostream>
@@ -32,7 +33,7 @@ namespace {
   Statistic<> NumStores("ra-simple", "Number of stores added");
   Statistic<> NumLoads ("ra-simple", "Number of loads added");
 
-  class RegAllocSimple : public MachineFunctionPass {
+  class VISIBILITY_HIDDEN RegAllocSimple : public MachineFunctionPass {
     MachineFunction *MF;
     const TargetMachine *TM;
     const MRegisterInfo *RegInfo;

lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp

@@ -26,6 +26,7 @@
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Support/Debug.h"
+#include "llvm/Support/Visibility.h"
 #include "llvm/ADT/Statistic.h"
 #include <climits>
 #include <iostream>
@@ -42,7 +43,7 @@ namespace {
 /// ScheduleDAGList - The actual list scheduler implementation.  This supports
 /// top-down scheduling.
 ///
-class ScheduleDAGList : public ScheduleDAG {
+class VISIBILITY_HIDDEN ScheduleDAGList : public ScheduleDAG {
 private:
   /// AvailableQueue - The priority queue to use for the available SUnits.
   ///

lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

@@ -23,6 +23,7 @@
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Support/Debug.h"
+#include "llvm/Support/Visibility.h"
 #include "llvm/ADT/Statistic.h"
 #include <climits>
 #include <iostream>
@@ -36,7 +37,7 @@ namespace {
 /// implementation.  This supports both top-down and bottom-up scheduling.
 ///
 
-class ScheduleDAGRRList : public ScheduleDAG {
+class VISIBILITY_HIDDEN ScheduleDAGRRList : public ScheduleDAG {
 private:
   /// isBottomUp - This is true if the scheduling problem is bottom-up, false if
   /// it is top-down.

lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp

@@ -20,6 +20,7 @@
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Support/Debug.h"
+#include "llvm/Support/Visibility.h"
 #include <algorithm>
 #include <iostream>
 using namespace llvm;
@@ -389,7 +390,7 @@ public:
 ///
 /// ScheduleDAGSimple - Simple two pass scheduler.
 ///
-class ScheduleDAGSimple : public ScheduleDAG {
+class VISIBILITY_HIDDEN ScheduleDAGSimple : public ScheduleDAG {
 private:
   bool NoSched;                         // Just do a BFS schedule, nothing fancy
   bool NoItins;                         // Don't use itineraries?

lib/CodeGen/TwoAddressInstructionPass.cpp

@@ -38,6 +38,7 @@
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Support/Debug.h"
+#include "llvm/Support/Visibility.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/ADT/STLExtras.h"
 #include <iostream>
@@ -51,7 +52,8 @@ namespace {
   Statistic<> NumConvertedTo3Addr("twoaddressinstruction",
                                 "Number of instructions promoted to 3-address");
 
-  struct TwoAddressInstructionPass : public MachineFunctionPass {
+  struct VISIBILITY_HIDDEN TwoAddressInstructionPass
+   : public MachineFunctionPass {
     virtual void getAnalysisUsage(AnalysisUsage &AU) const;
 
     /// runOnMachineFunction - pass entry point

lib/CodeGen/VirtRegMap.cpp

@@ -26,6 +26,7 @@
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
+#include "llvm/Support/Visibility.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/ADT/STLExtras.h"
 #include <algorithm>
@@ -130,7 +131,7 @@ void VirtRegMap::dump() const { print(std::cerr); }
 Spiller::~Spiller() {}
 
 namespace {
-  struct SimpleSpiller : public Spiller {
+  struct VISIBILITY_HIDDEN SimpleSpiller : public Spiller {
     bool runOnMachineFunction(MachineFunction& mf, VirtRegMap &VRM);
   };
 }
@@ -204,7 +205,7 @@ namespace {
   /// block to attempt to keep spills in registers as much as possible for
   /// blocks that have low register pressure (the vreg may be spilled due to
   /// register pressure in other blocks).
-  class LocalSpiller : public Spiller {
+  class VISIBILITY_HIDDEN LocalSpiller : public Spiller {
     const MRegisterInfo *MRI;
     const TargetInstrInfo *TII;
   public:
@@ -240,7 +241,8 @@ namespace {
 /// per-stack-slot basis as the low bit in the value of the SpillSlotsAvailable
 /// entries.  The predicate 'canClobberPhysReg()' checks this bit and
 /// addAvailable sets it if.
-class AvailableSpills {
+namespace {
+class VISIBILITY_HIDDEN AvailableSpills {
   const MRegisterInfo *MRI;
   const TargetInstrInfo *TII;
 
@@ -304,6 +306,7 @@ public:
   /// for this slot lives in (as the previous value is dead now).
   void ModifyStackSlot(int Slot);
 };
+}
 
 /// ClobberPhysRegOnly - This is called when the specified physreg changes
 /// value.  We use this to invalidate any info about stuff we thing lives in it.
@@ -379,7 +382,7 @@ namespace {
   
   /// ReuseInfo - This maintains a collection of ReuseOp's for each operand that
   /// is reused instead of reloaded.
-  class ReuseInfo {
+  class VISIBILITY_HIDDEN ReuseInfo {
     MachineInstr &MI;
     std::vector<ReusedOp> Reuses;
   public: