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Remove unnecessary type check when combining and/or/xor of swizzles. Move some checks to allow better early out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154309 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2361,18 +2361,16 @@ SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
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// The type-legalizer generates this pattern when loading illegal
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// vector types from memory. In many cases this allows additional shuffle
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// optimizations.
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if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG) {
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if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
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N0.getOperand(1).getOpcode() == ISD::UNDEF &&
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N1.getOperand(1).getOpcode() == ISD::UNDEF) {
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ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(N0);
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ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(N1);
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SDValue In0 = SVN0->getOperand(0);
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SDValue In1 = SVN1->getOperand(0);
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EVT In0Ty = In0.getValueType();
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EVT In1Ty = In1.getValueType();
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assert(N0.getOperand(0).getValueType() == N1.getOperand(1).getValueType() &&
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"Inputs to shuffles are not the same type");
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unsigned NumElts = VT.getVectorNumElements();
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// Check that both shuffles are swizzles.
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bool SingleVecShuff = (N0.getOperand(1).getOpcode() == ISD::UNDEF &&
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N1.getOperand(1).getOpcode() == ISD::UNDEF);
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// Check that both shuffles use the same mask. The masks are known to be of
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// the same length because the result vector type is the same.
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@ -2386,14 +2384,15 @@ SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
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}
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}
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if (SameMask && SingleVecShuff && In0Ty == In1Ty) {
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SDValue Op = DAG.getNode(N->getOpcode(), N->getDebugLoc(), VT, In0, In1);
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SDValue Shuff = DAG.getVectorShuffle(VT, N->getDebugLoc(), Op,
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DAG.getUNDEF(VT), &SVN0->getMask()[0]);
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if (SameMask) {
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SDValue Op = DAG.getNode(N->getOpcode(), N->getDebugLoc(), VT,
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N0.getOperand(0), N1.getOperand(0));
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AddToWorkList(Op.getNode());
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return Shuff;
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return DAG.getVectorShuffle(VT, N->getDebugLoc(), Op,
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DAG.getUNDEF(VT), &SVN0->getMask()[0]);
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}
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}
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return SDValue();
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}
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