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ARM itinerary properties.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157980 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick
2012-06-05 03:44:43 +00:00
parent fc992996f7
commit f94f051cf5
3 changed files with 10 additions and 22 deletions
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6
lib/Target/ARM/ARMScheduleA8.td
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@@ -22,7 +22,11 @@ def A8_NLSPipe : FuncUnit; // NEON LS pipe
//
// Dual issue pipeline represented by A8_Pipe0 | A8_Pipe1
//
def CortexA8Itineraries : ProcessorItineraries<
def CortexA8Itineraries : MultiIssueItineraries<
2, // IssueWidth
-1, // MinLatency - OperandCycles are interpreted as MinLatency.
2, // LoadLatency - overriden by OperandCycles.
10, // HighLatency - currently unused.
[A8_Pipe0, A8_Pipe1, A8_LSPipe, A8_NPipe, A8_NLSPipe],
[], [
// Two fully-pipelined integer ALU pipelines