6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-11-16 11:05:54 +00:00
Code Issues Projects Releases Wiki Activity

Add missing explicit writeback operand to tSTMIA_UPD.

Browse Source 
rdar://10014745

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138457 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-08-24 18:19:42 +00:00
parent 3e74d6fdd2
commit f95aaf951b
2 changed files with 5 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
lib/Target/ARM/ARMInstrThumb.td
View File

@ -726,9 +726,10 @@ def tLDMIA_UPD :
// There is no non-writeback version of STM for Thumb.
let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
def tSTMIA_UPD : T1I<(outs),
(ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
IIC_iStore_mu, "stm${p}\t$Rn!, $regs", []>,
def tSTMIA_UPD : Thumb1I<(outs GPR:$wb),
(ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
AddrModeNone, 2, IIC_iStore_mu,
"stm${p}\t$Rn!, $regs", "$Rn = $wb", []>,
T1Encoding<{1,1,0,0,0,?}> {
bits<3> Rn;
bits<8> regs;

2
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -3152,7 +3152,7 @@ validateInstruction(MCInst &Inst,
}
case ARM::tSTMIA_UPD: {
bool listContainsBase;
if (checkLowRegisterList(Inst, 3, 0, 0, listContainsBase))
if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase))
return Error(Operands[4]->getStartLoc(),
"registers must be in range r0-r7");
break;