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Compute lists of super-classes in CodeGenRegisterClass.

Browse Source 
Use these lists instead of computing them on the fly in
RegisterInfoEmitter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140895 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2011-09-30 22:18:45 +00:00
parent f391e9f696
commit f9a4bb78da
3 changed files with 43 additions and 39 deletions
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10
utils/TableGen/CodeGenRegisters.cpp
View File

@ -414,6 +414,16 @@ computeSubClasses(ArrayRef<CodeGenRegisterClass*> RegClasses) {
for (unsigned s = rci - 1; s && RC.hasSubClass(RegClasses[s - 1]); --s)
RC.SubClasses.set(s - 1);
}
// Compute the SuperClasses lists from the SubClasses vectors.
for (unsigned rci = 0; rci != RegClasses.size(); ++rci) {
const BitVector &SC = RegClasses[rci]->getSubClasses();
for (int s = SC.find_first(); s >= 0; s = SC.find_next(s)) {
if (unsigned(s) == rci)
continue;
RegClasses[s]->SuperClasses.push_back(RegClasses[rci]);
}
}
}
//===----------------------------------------------------------------------===//

14
utils/TableGen/CodeGenRegisters.h
View File

@ -90,6 +90,9 @@ namespace llvm {
std::vector<SmallVector<Record*, 16> > AltOrders;
// Bit mask of sub-classes including this, indexed by their EnumValue.
BitVector SubClasses;
// List of super-classes, topologocally ordered to have the larger classes
// first. This is the same as sorting by EnumValue.
SmallVector<CodeGenRegisterClass*, 4> SuperClasses;
public:
Record *TheDef;
unsigned EnumValue;
@ -128,6 +131,17 @@ namespace llvm {
//
bool hasSubClass(const CodeGenRegisterClass *RC) const;
// getSubClasses - Returns a constant BitVector of subclasses indexed by
// EnumValue.
// The SubClasses vector includs an entry for this class.
const BitVector &getSubClasses() const { return SubClasses; };
// getSuperClasses - Returns a list of super classes ordered by EnumValue.
// The array does not include an entry for this class.
ArrayRef<CodeGenRegisterClass*> getSuperClasses() const {
return SuperClasses;
}
// Returns an ordered list of class members.
// The order of registers is the same as in the .td file.
// No = 0 is the default allocation order, No = 1 is the first alternative.

58
utils/TableGen/RegisterInfoEmitter.cpp
View File

@ -527,9 +527,10 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
OS << " " << RegisterClasses[i]->getName() << "Class\t"
<< RegisterClasses[i]->getName() << "RegClass;\n";
std::map<unsigned, std::set<unsigned> > SuperClassMap;
std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
OS << "\n";
OS << "\n static const TargetRegisterClass* const "
<< "NullRegClasses[] = { NULL };\n\n";
unsigned NumSubRegIndices = RegBank.getSubRegIndices().size();
@ -603,10 +604,6 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
OS << (!Empty ? ", " : "") << "NULL";
OS << "\n };\n\n";
}
} else {
// No subregindices in this target
OS << " static const TargetRegisterClass* const "
<< "NullRegClasses[] = { NULL };\n\n";
}
// Emit the sub-classes array for each RegisterClass
@ -632,46 +629,26 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
if (!Empty) OS << ", ";
OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
Empty = false;
std::map<unsigned, std::set<unsigned> >::iterator SCMI =
SuperClassMap.find(rc2);
if (SCMI == SuperClassMap.end()) {
SuperClassMap.insert(std::make_pair(rc2, std::set<unsigned>()));
SCMI = SuperClassMap.find(rc2);
}
SCMI->second.insert(rc);
}
OS << (!Empty ? ", " : "") << "NULL";
OS << "\n };\n\n";
}
// Emit NULL terminated super-class lists.
for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
const CodeGenRegisterClass &RC = *RegisterClasses[rc];
ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses();
// Give the register class a legal C name if it's anonymous.
std::string Name = RC.TheDef->getName();
// Skip classes without supers. We can reuse NullRegClasses.
if (Supers.empty())
continue;
OS << " // " << Name
<< " Register Class super-classes...\n"
<< " static const TargetRegisterClass* const "
<< Name << "Superclasses[] = {\n ";
bool Empty = true;
std::map<unsigned, std::set<unsigned> >::iterator I =
SuperClassMap.find(rc);
if (I != SuperClassMap.end()) {
for (std::set<unsigned>::iterator II = I->second.begin(),
EE = I->second.end(); II != EE; ++II) {
const CodeGenRegisterClass &RC2 = *RegisterClasses[*II];
if (!Empty) OS << ", ";
OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
Empty = false;
}
}
OS << (!Empty ? ", " : "") << "NULL";
OS << "\n };\n\n";
OS << " static const TargetRegisterClass* const "
<< RC.getName() << "Superclasses[] = {\n";
for (unsigned i = 0; i != Supers.size(); ++i)
OS << " &" << getQualifiedName(Supers[i]->TheDef) << "RegClass,\n";
OS << " NULL\n };\n\n";
}
// Emit methods.
@ -682,9 +659,12 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
<< Target.getName() << "MCRegisterClasses["
<< RC.getName() + "RegClassID" << "], "
<< RC.getName() + "VTs" << ", "
<< RC.getName() + "Subclasses" << ", "
<< RC.getName() + "Superclasses" << ", "
<< (NumSubRegIndices ? RC.getName() + "Sub" : std::string("Null"))
<< RC.getName() + "Subclasses" << ", ";
if (RC.getSuperClasses().empty())
OS << "NullRegClasses, ";
else
OS << RC.getName() + "Superclasses, ";
OS << (NumSubRegIndices ? RC.getName() + "Sub" : std::string("Null"))
<< "RegClasses, "
<< (NumSubRegIndices ? RC.getName() + "Super" : std::string("Null"))
<< "RegClasses"