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Compute lists of super-classes in CodeGenRegisterClass.
Use these lists instead of computing them on the fly in RegisterInfoEmitter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140895 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -414,6 +414,16 @@ computeSubClasses(ArrayRef<CodeGenRegisterClass*> RegClasses) {
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for (unsigned s = rci - 1; s && RC.hasSubClass(RegClasses[s - 1]); --s)
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for (unsigned s = rci - 1; s && RC.hasSubClass(RegClasses[s - 1]); --s)
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RC.SubClasses.set(s - 1);
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RC.SubClasses.set(s - 1);
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}
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}
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// Compute the SuperClasses lists from the SubClasses vectors.
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for (unsigned rci = 0; rci != RegClasses.size(); ++rci) {
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const BitVector &SC = RegClasses[rci]->getSubClasses();
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for (int s = SC.find_first(); s >= 0; s = SC.find_next(s)) {
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if (unsigned(s) == rci)
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continue;
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RegClasses[s]->SuperClasses.push_back(RegClasses[rci]);
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}
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}
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}
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}
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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@ -90,6 +90,9 @@ namespace llvm {
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std::vector<SmallVector<Record*, 16> > AltOrders;
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std::vector<SmallVector<Record*, 16> > AltOrders;
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// Bit mask of sub-classes including this, indexed by their EnumValue.
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// Bit mask of sub-classes including this, indexed by their EnumValue.
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BitVector SubClasses;
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BitVector SubClasses;
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// List of super-classes, topologocally ordered to have the larger classes
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// first. This is the same as sorting by EnumValue.
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SmallVector<CodeGenRegisterClass*, 4> SuperClasses;
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public:
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public:
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Record *TheDef;
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Record *TheDef;
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unsigned EnumValue;
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unsigned EnumValue;
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@ -128,6 +131,17 @@ namespace llvm {
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//
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//
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bool hasSubClass(const CodeGenRegisterClass *RC) const;
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bool hasSubClass(const CodeGenRegisterClass *RC) const;
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// getSubClasses - Returns a constant BitVector of subclasses indexed by
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// EnumValue.
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// The SubClasses vector includs an entry for this class.
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const BitVector &getSubClasses() const { return SubClasses; };
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// getSuperClasses - Returns a list of super classes ordered by EnumValue.
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// The array does not include an entry for this class.
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ArrayRef<CodeGenRegisterClass*> getSuperClasses() const {
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return SuperClasses;
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}
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// Returns an ordered list of class members.
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// Returns an ordered list of class members.
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// The order of registers is the same as in the .td file.
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// The order of registers is the same as in the .td file.
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// No = 0 is the default allocation order, No = 1 is the first alternative.
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// No = 0 is the default allocation order, No = 1 is the first alternative.
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@ -527,9 +527,10 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
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OS << " " << RegisterClasses[i]->getName() << "Class\t"
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OS << " " << RegisterClasses[i]->getName() << "Class\t"
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<< RegisterClasses[i]->getName() << "RegClass;\n";
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<< RegisterClasses[i]->getName() << "RegClass;\n";
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std::map<unsigned, std::set<unsigned> > SuperClassMap;
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std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
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std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
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OS << "\n";
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OS << "\n static const TargetRegisterClass* const "
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<< "NullRegClasses[] = { NULL };\n\n";
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unsigned NumSubRegIndices = RegBank.getSubRegIndices().size();
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unsigned NumSubRegIndices = RegBank.getSubRegIndices().size();
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@ -603,10 +604,6 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
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OS << (!Empty ? ", " : "") << "NULL";
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OS << (!Empty ? ", " : "") << "NULL";
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OS << "\n };\n\n";
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OS << "\n };\n\n";
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}
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}
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} else {
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// No subregindices in this target
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OS << " static const TargetRegisterClass* const "
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<< "NullRegClasses[] = { NULL };\n\n";
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}
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}
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// Emit the sub-classes array for each RegisterClass
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// Emit the sub-classes array for each RegisterClass
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@ -632,46 +629,26 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
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if (!Empty) OS << ", ";
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if (!Empty) OS << ", ";
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OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
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OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
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Empty = false;
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Empty = false;
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std::map<unsigned, std::set<unsigned> >::iterator SCMI =
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SuperClassMap.find(rc2);
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if (SCMI == SuperClassMap.end()) {
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SuperClassMap.insert(std::make_pair(rc2, std::set<unsigned>()));
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SCMI = SuperClassMap.find(rc2);
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}
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SCMI->second.insert(rc);
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}
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}
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OS << (!Empty ? ", " : "") << "NULL";
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OS << (!Empty ? ", " : "") << "NULL";
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OS << "\n };\n\n";
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OS << "\n };\n\n";
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}
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}
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// Emit NULL terminated super-class lists.
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for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
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for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
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const CodeGenRegisterClass &RC = *RegisterClasses[rc];
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const CodeGenRegisterClass &RC = *RegisterClasses[rc];
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ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses();
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// Give the register class a legal C name if it's anonymous.
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// Skip classes without supers. We can reuse NullRegClasses.
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std::string Name = RC.TheDef->getName();
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if (Supers.empty())
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continue;
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OS << " // " << Name
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OS << " static const TargetRegisterClass* const "
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<< " Register Class super-classes...\n"
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<< RC.getName() << "Superclasses[] = {\n";
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<< " static const TargetRegisterClass* const "
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for (unsigned i = 0; i != Supers.size(); ++i)
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<< Name << "Superclasses[] = {\n ";
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OS << " &" << getQualifiedName(Supers[i]->TheDef) << "RegClass,\n";
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OS << " NULL\n };\n\n";
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bool Empty = true;
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std::map<unsigned, std::set<unsigned> >::iterator I =
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SuperClassMap.find(rc);
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if (I != SuperClassMap.end()) {
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for (std::set<unsigned>::iterator II = I->second.begin(),
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EE = I->second.end(); II != EE; ++II) {
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const CodeGenRegisterClass &RC2 = *RegisterClasses[*II];
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if (!Empty) OS << ", ";
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OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
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Empty = false;
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}
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}
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OS << (!Empty ? ", " : "") << "NULL";
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OS << "\n };\n\n";
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}
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}
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// Emit methods.
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// Emit methods.
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@ -682,9 +659,12 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
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<< Target.getName() << "MCRegisterClasses["
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<< Target.getName() << "MCRegisterClasses["
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<< RC.getName() + "RegClassID" << "], "
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<< RC.getName() + "RegClassID" << "], "
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<< RC.getName() + "VTs" << ", "
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<< RC.getName() + "VTs" << ", "
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<< RC.getName() + "Subclasses" << ", "
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<< RC.getName() + "Subclasses" << ", ";
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<< RC.getName() + "Superclasses" << ", "
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if (RC.getSuperClasses().empty())
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<< (NumSubRegIndices ? RC.getName() + "Sub" : std::string("Null"))
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OS << "NullRegClasses, ";
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else
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OS << RC.getName() + "Superclasses, ";
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OS << (NumSubRegIndices ? RC.getName() + "Sub" : std::string("Null"))
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<< "RegClasses, "
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<< "RegClasses, "
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<< (NumSubRegIndices ? RC.getName() + "Super" : std::string("Null"))
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<< (NumSubRegIndices ? RC.getName() + "Super" : std::string("Null"))
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<< "RegClasses"
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<< "RegClasses"
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