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[mips][microMIPS] Implement microMIPS 16-bit instructions registers

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Differential Revision: http://reviews.llvm.org/D5116


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220273 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Zoran Jovanovic 2014-10-21 08:23:11 +00:00
parent 45968c54e9
commit fa20aa343b
3 changed files with 46 additions and 0 deletions
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19
lib/Target/Mips/AsmParser/MipsAsmParser.cpp
View File

@ -492,6 +492,14 @@ public:
return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
}
/// Coerce the register to GPR32 and return the real register for the current
/// target.
unsigned getGPRMM16Reg() const {
assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!");
unsigned ClassID = Mips::GPR32RegClassID;
return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
}
/// Coerce the register to GPR64 and return the real register for the current
/// target.
unsigned getGPR64Reg() const {
@ -640,6 +648,11 @@ public:
Inst.addOperand(MCOperand::CreateReg(getGPR32Reg()));
}
void addGPRMM16AsmRegOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
Inst.addOperand(MCOperand::CreateReg(getGPRMM16Reg()));
}
/// Render the operand to an MCInst as a GPR64
/// Asserts if the wrong number of operands are requested, or the operand
/// is not a k_RegisterIndex compatible with RegKind_GPR
@ -900,6 +913,12 @@ public:
bool isGPRAsmReg() const {
return isRegIdx() && RegIdx.Kind & RegKind_GPR && RegIdx.Index <= 31;
}
bool isMM16AsmReg() const {
if (!(isRegIdx() && RegIdx.Kind))
return false;
return ((RegIdx.Index >= 2 && RegIdx.Index <= 7)
|| RegIdx.Index == 16 || RegIdx.Index == 17);
}
bool isFGRAsmReg() const {
// AFGR64 is $0-$15 but we handle this in getAFGR64()
return isRegIdx() && RegIdx.Kind & RegKind_FGR && RegIdx.Index <= 31;

12
lib/Target/Mips/Disassembler/MipsDisassembler.cpp
View File

@ -117,6 +117,11 @@ static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
@ -870,6 +875,13 @@ static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
return MCDisassembler::Success;
}
static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
return MCDisassembler::Fail;
}
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,

15
lib/Target/Mips/MipsRegisterInfo.td
View File

@ -283,6 +283,12 @@ class GPR32Class<list<ValueType> regTypes> :
def GPR32 : GPR32Class<[i32]>;
def DSPR : GPR32Class<[v4i8, v2i16]>;
def GPRMM16 : RegisterClass<"Mips", [i32], 32, (add
// Return Values and Arguments
V0, V1, A0, A1, A2, A3,
// Callee save
S0, S1)>;
def GPR64 : RegisterClass<"Mips", [i64], 64, (add
// Reserved
ZERO_64, AT_64,
@ -430,6 +436,11 @@ def GPR32AsmOperand : MipsAsmRegOperand {
let PredicateMethod = "isGPRAsmReg";
}
def GPRMM16AsmOperand : MipsAsmRegOperand {
let Name = "GPRMM16AsmReg";
let PredicateMethod = "isMM16AsmReg";
}
def ACC64DSPAsmOperand : MipsAsmRegOperand {
let Name = "ACC64DSPAsmReg";
let PredicateMethod = "isACCAsmReg";
@ -485,6 +496,10 @@ def GPR32Opnd : RegisterOperand<GPR32> {
let ParserMatchClass = GPR32AsmOperand;
}
def GPRMM16Opnd : RegisterOperand<GPRMM16> {
let ParserMatchClass = GPRMM16AsmOperand;
}
def GPR64Opnd : RegisterOperand<GPR64> {
let ParserMatchClass = GPR64AsmOperand;
}