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ARM64: Extended addressing mode source reg is 64-bit.

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The canonical form for the extended addressing mode (e.g.,
"[x1, w2, uxtw #3]" is for the MCInst to have the second register be the
full 64-bit GPR64 register class. The instruction printer cleans up
the output for display to show the 32-bit register instead, per the
specification.

This simplifies 205893 now that the aliasing is handled in the printer
in 206495 so that the codegen path and the disassembler path give the
same MCInst form.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206797 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2014-04-21 21:45:44 +00:00
parent e1c0863d74
commit fa49d1ade6
1 changed files with 1 additions and 5 deletions
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6
lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
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@ -1182,11 +1182,7 @@ static DecodeStatus DecodeRegOffsetLdStInstruction(llvm::MCInst &Inst,
}
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
if ((extendHi & 0x3) == 0x3)
DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
else
DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
Inst.addOperand(MCOperand::CreateImm(extend));
return Success;