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Undo 48570. Correctly match mmx shift instructions with an immediate operand.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48627 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2008-03-21 00:40:09 +00:00
parent 2197b8092c
commit fa5a91a71e
4 changed files with 27 additions and 44 deletions
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24
include/llvm/IntrinsicsX86.td
View File

@ -916,53 +916,29 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_mmx_psll_w : GCCBuiltin<"__builtin_ia32_psllw">, def int_x86_mmx_psll_w : GCCBuiltin<"__builtin_ia32_psllw">,
Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty, Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty,
llvm_v1i64_ty], [IntrNoMem]>; llvm_v1i64_ty], [IntrNoMem]>;
def int_x86_mmx_pslli_w : GCCBuiltin<"__builtin_ia32_psllwi">,
Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty,
llvm_i32_ty], [IntrNoMem]>;
def int_x86_mmx_psll_d : GCCBuiltin<"__builtin_ia32_pslld">, def int_x86_mmx_psll_d : GCCBuiltin<"__builtin_ia32_pslld">,
Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty, Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty,
llvm_v1i64_ty], [IntrNoMem]>; llvm_v1i64_ty], [IntrNoMem]>;
def int_x86_mmx_pslli_d : GCCBuiltin<"__builtin_ia32_pslldi">,
Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty,
llvm_i32_ty], [IntrNoMem]>;
def int_x86_mmx_psll_q : GCCBuiltin<"__builtin_ia32_psllq">, def int_x86_mmx_psll_q : GCCBuiltin<"__builtin_ia32_psllq">,
Intrinsic<[llvm_v1i64_ty, llvm_v1i64_ty, Intrinsic<[llvm_v1i64_ty, llvm_v1i64_ty,
llvm_v1i64_ty], [IntrNoMem]>; llvm_v1i64_ty], [IntrNoMem]>;
def int_x86_mmx_pslli_q : GCCBuiltin<"__builtin_ia32_psllqi">,
Intrinsic<[llvm_v1i64_ty, llvm_v1i64_ty,
llvm_i32_ty], [IntrNoMem]>;
def int_x86_mmx_psrl_w : GCCBuiltin<"__builtin_ia32_psrlw">, def int_x86_mmx_psrl_w : GCCBuiltin<"__builtin_ia32_psrlw">,
Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty, Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty,
llvm_v1i64_ty], [IntrNoMem]>; llvm_v1i64_ty], [IntrNoMem]>;
def int_x86_mmx_psrli_w : GCCBuiltin<"__builtin_ia32_psrlwi">,
Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty,
llvm_i32_ty], [IntrNoMem]>;
def int_x86_mmx_psrl_d : GCCBuiltin<"__builtin_ia32_psrld">, def int_x86_mmx_psrl_d : GCCBuiltin<"__builtin_ia32_psrld">,
Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty, Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty,
llvm_v1i64_ty], [IntrNoMem]>; llvm_v1i64_ty], [IntrNoMem]>;
def int_x86_mmx_psrli_d : GCCBuiltin<"__builtin_ia32_psrldi">,
Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty,
llvm_i32_ty], [IntrNoMem]>;
def int_x86_mmx_psrl_q : GCCBuiltin<"__builtin_ia32_psrlq">, def int_x86_mmx_psrl_q : GCCBuiltin<"__builtin_ia32_psrlq">,
Intrinsic<[llvm_v1i64_ty, llvm_v1i64_ty, Intrinsic<[llvm_v1i64_ty, llvm_v1i64_ty,
llvm_v1i64_ty], [IntrNoMem]>; llvm_v1i64_ty], [IntrNoMem]>;
def int_x86_mmx_psrli_q : GCCBuiltin<"__builtin_ia32_psrlqi">,
Intrinsic<[llvm_v1i64_ty, llvm_v1i64_ty,
llvm_i32_ty], [IntrNoMem]>;
def int_x86_mmx_psra_w : GCCBuiltin<"__builtin_ia32_psraw">, def int_x86_mmx_psra_w : GCCBuiltin<"__builtin_ia32_psraw">,
Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty, Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty,
llvm_v1i64_ty], [IntrNoMem]>; llvm_v1i64_ty], [IntrNoMem]>;
def int_x86_mmx_psrai_w : GCCBuiltin<"__builtin_ia32_psrawi">,
Intrinsic<[llvm_v4i16_ty, llvm_v4i16_ty,
llvm_i32_ty], [IntrNoMem]>;
def int_x86_mmx_psra_d : GCCBuiltin<"__builtin_ia32_psrad">, def int_x86_mmx_psra_d : GCCBuiltin<"__builtin_ia32_psrad">,
Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty, Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty,
llvm_v1i64_ty], [IntrNoMem]>; llvm_v1i64_ty], [IntrNoMem]>;
def int_x86_mmx_psrai_d : GCCBuiltin<"__builtin_ia32_psradi">,
Intrinsic<[llvm_v2i32_ty, llvm_v2i32_ty,
llvm_i32_ty], [IntrNoMem]>;
} }
// Pack ops. // Pack ops.

40
lib/Target/X86/X86InstrMMX.td
View File

@ -104,30 +104,38 @@ let isTwoAddress = 1 in {
// //
multiclass MMXI_binop_rm_v1i64<bits<8> opc, string OpcodeStr, SDNode OpNode, multiclass MMXI_binop_rm_v1i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
bit Commutable = 0> { bit Commutable = 0> {
def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2), def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
(ins VR64:$src1, VR64:$src2),
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
[(set VR64:$dst, (v1i64 (OpNode VR64:$src1, VR64:$src2)))]> { [(set VR64:$dst, (v1i64 (OpNode VR64:$src1, VR64:$src2)))]> {
let isCommutable = Commutable; let isCommutable = Commutable;
} }
def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2), def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
(ins VR64:$src1, i64mem:$src2),
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
[(set VR64:$dst, [(set VR64:$dst,
(OpNode VR64:$src1,(load_mmx addr:$src2)))]>; (OpNode VR64:$src1,(load_mmx addr:$src2)))]>;
} }
multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm, multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
string OpcodeStr, Intrinsic IntId, string OpcodeStr, Intrinsic IntId> {
Intrinsic ImmIntId> { def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2), (ins VR64:$src1, VR64:$src2),
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
[(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>; [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>;
def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2), def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
(ins VR64:$src1, i64mem:$src2),
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
[(set VR64:$dst, (IntId VR64:$src1, [(set VR64:$dst, (IntId VR64:$src1,
(bitconvert (load_mmx addr:$src2))))]>; (bitconvert (load_mmx addr:$src2))))]>;
def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst), (ins VR64:$src1, i32i8imm:$src2), def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst),
(ins VR64:$src1, i32i8imm:$src2),
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
[(set VR64:$dst, (ImmIntId VR64:$src1, imm:$src2))]>; [(set VR64:$dst, (IntId VR64:$src1,
(v1i64 (bitconvert
(v2i32 (vector_shuffle immAllZerosV,
(v2i32 (scalar_to_vector (i32 imm:$src2))),
MMX_MOVL_shuffle_mask))))))]>;
} }
} }
@ -268,23 +276,23 @@ let isTwoAddress = 1 in {
// Shift Instructions // Shift Instructions
defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw", defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
int_x86_mmx_psrl_w, int_x86_mmx_psrli_w>; int_x86_mmx_psrl_w>;
defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld", defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
int_x86_mmx_psrl_d, int_x86_mmx_psrli_d>; int_x86_mmx_psrl_d>;
defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq", defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
int_x86_mmx_psrl_q, int_x86_mmx_psrli_q>; int_x86_mmx_psrl_q>;
defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw", defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
int_x86_mmx_psll_w, int_x86_mmx_pslli_w>; int_x86_mmx_psll_w>;
defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld", defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
int_x86_mmx_psll_d, int_x86_mmx_pslli_d>; int_x86_mmx_psll_d>;
defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq", defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
int_x86_mmx_psll_q, int_x86_mmx_pslli_q>; int_x86_mmx_psll_q>;
defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw", defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
int_x86_mmx_psra_w, int_x86_mmx_psrai_w>; int_x86_mmx_psra_w>;
defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad", defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
int_x86_mmx_psra_d, int_x86_mmx_psrai_d>; int_x86_mmx_psra_d>;
// Comparison Instructions // Comparison Instructions
defm MMX_PCMPEQB : MMXI_binop_rm_int<0x74, "pcmpeqb", int_x86_mmx_pcmpeq_b>; defm MMX_PCMPEQB : MMXI_binop_rm_int<0x74, "pcmpeqb", int_x86_mmx_pcmpeq_b>;

3
lib/VMCore/AutoUpgrade.cpp
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@ -122,8 +122,7 @@ static bool UpgradeIntrinsicFunction1(Function *F, Function *&NewFn) {
if (Name.compare(5,10,"x86.mmx.ps",10) == 0 && if (Name.compare(5,10,"x86.mmx.ps",10) == 0 &&
(Name.compare(13,4,"psll", 4) == 0 || (Name.compare(13,4,"psll", 4) == 0 ||
Name.compare(13,4,"psra", 4) == 0 || Name.compare(13,4,"psra", 4) == 0 ||
Name.compare(13,4,"psrl", 4) == 0) && Name.compare(13,4,"psrl", 4) == 0)) {
Name[17] != 'i') {
const llvm::Type *VT = VectorType::get(IntegerType::get(64), 1); const llvm::Type *VT = VectorType::get(IntegerType::get(64), 1);

4
test/CodeGen/X86/mmx-shift.ll
View File

@ -3,12 +3,12 @@
define i64 @t1(<1 x i64> %mm1) nounwind { define i64 @t1(<1 x i64> %mm1) nounwind {
entry: entry:
%tmp6 = tail call <1 x i64> @llvm.x86.mmx.pslli.q( <1 x i64> %mm1, i32 32 ) ; <<1 x i64>> [#uses=1] %tmp6 = tail call <1 x i64> @llvm.x86.mmx.psll.q( <1 x i64> %mm1, <1 x i64> <i64 32> ) ; <<1 x i64>> [#uses=1]
%retval1112 = bitcast <1 x i64> %tmp6 to i64 ; <i64> [#uses=1] %retval1112 = bitcast <1 x i64> %tmp6 to i64 ; <i64> [#uses=1]
ret i64 %retval1112 ret i64 %retval1112
} }
declare <1 x i64> @llvm.x86.mmx.pslli.q(<1 x i64>, i32) nounwind readnone declare <1 x i64> @llvm.x86.mmx.psll.q(<1 x i64>, <1 x i64>) nounwind readnone
define i64 @t2(<2 x i32> %mm1, <2 x i32> %mm2) nounwind { define i64 @t2(<2 x i32> %mm1, <2 x i32> %mm2) nounwind {
entry: entry: