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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82442 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -220,7 +220,20 @@ so cool to turn it into something like:
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... which would only do one 32-bit XOR per loop iteration instead of two.
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... which would only do one 32-bit XOR per loop iteration instead of two.
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It would also be nice to recognize the reg->size doesn't alias reg->node[i], but
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It would also be nice to recognize the reg->size doesn't alias reg->node[i], but
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alas...
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alas.
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//===---------------------------------------------------------------------===//
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This should be optimized to one 'and' and one 'or', from PR4216:
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define i32 @test_bitfield(i32 %bf.prev.low) nounwind ssp {
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entry:
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%bf.prev.lo.cleared10 = or i32 %bf.prev.low, 32962 ; <i32> [#uses=1]
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%0 = and i32 %bf.prev.low, -65536 ; <i32> [#uses=1]
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%1 = and i32 %bf.prev.lo.cleared10, 40186 ; <i32> [#uses=1]
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%2 = or i32 %1, %0 ; <i32> [#uses=1]
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ret i32 %2
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}
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//===---------------------------------------------------------------------===//
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//===---------------------------------------------------------------------===//
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