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More ppcf128 issues (maybe the last)?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43160 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -20,6 +20,10 @@ namespace RTLIB {
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/// RTLIB::Libcall enum - This enum defines all of the runtime library calls
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/// RTLIB::Libcall enum - This enum defines all of the runtime library calls
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/// the backend can emit. The various long double types cannot be merged,
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/// the backend can emit. The various long double types cannot be merged,
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/// because 80-bit library functions use "xf" and 128-bit use "tf".
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/// because 80-bit library functions use "xf" and 128-bit use "tf".
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///
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/// When adding PPCF128 functions here, note that their names generally need
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/// to be overridden for Darwin with the xxx$LDBL128 form. See
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/// PPCISelLowering.cpp.
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///
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///
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enum Libcall {
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enum Libcall {
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// Integer
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// Integer
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@ -3493,7 +3493,7 @@ SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
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return DAG.getNode(ISD::FP_EXTEND, VT, N0);
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return DAG.getNode(ISD::FP_EXTEND, VT, N0);
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// fold (fpext (load x)) -> (fpext (fpround (extload x)))
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// fold (fpext (load x)) -> (fpext (fpround (extload x)))
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if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
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if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && VT != MVT::ppcf128 &&
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(!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
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(!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
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LoadSDNode *LN0 = cast<LoadSDNode>(N0);
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LoadSDNode *LN0 = cast<LoadSDNode>(N0);
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SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
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SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
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@ -341,6 +341,13 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
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setTargetDAGCombine(ISD::BR_CC);
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setTargetDAGCombine(ISD::BR_CC);
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setTargetDAGCombine(ISD::BSWAP);
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setTargetDAGCombine(ISD::BSWAP);
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// Darwin long double math library functions have $LDBL128 appended.
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if (TM.getSubtarget<PPCSubtarget>().isDarwin()) {
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setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
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setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
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setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
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}
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computeRegisterProperties();
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computeRegisterProperties();
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}
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}
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