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https://github.com/c64scene-ar/llvm-6502.git
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Reduce uses of getRegClass
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15973 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -44,13 +44,13 @@ namespace {
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X86RegisterInfo::X86RegisterInfo()
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: X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP) {}
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static unsigned getIdx(const TargetRegisterClass *RC) {
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switch (RC->getSize()) {
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static unsigned getIdx(unsigned SpillSize) {
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switch (SpillSize) {
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default: assert(0 && "Invalid data size!");
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case 1: return 0;
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case 2: return 1;
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case 4: return 2;
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case 10: return 3;
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case 8: return 0;
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case 16: return 1;
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case 32: return 2;
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case 80: return 3;
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}
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}
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@ -59,10 +59,8 @@ void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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unsigned SrcReg, int FrameIdx) const {
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static const unsigned Opcode[] =
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{ X86::MOV8mr, X86::MOV16mr, X86::MOV32mr, X86::FSTP80m };
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const TargetRegisterClass *RC = getRegClass(SrcReg);
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MachineInstr *I = addFrameReference(BuildMI(Opcode[getIdx(RC)], 5),
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FrameIdx).addReg(SrcReg);
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MBB.insert(MI, I);
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unsigned Idx = getIdx(getSpillSize(SrcReg));
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addFrameReference(BuildMI(MBB, MI, Opcode[Idx], 5), FrameIdx).addReg(SrcReg);
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}
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void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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@ -70,9 +68,8 @@ void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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unsigned DestReg, int FrameIdx)const{
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static const unsigned Opcode[] =
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{ X86::MOV8rm, X86::MOV16rm, X86::MOV32rm, X86::FLD80m };
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const TargetRegisterClass *RC = getRegClass(DestReg);
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unsigned OC = Opcode[getIdx(RC)];
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MBB.insert(MI, addFrameReference(BuildMI(OC, 4, DestReg), FrameIdx));
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unsigned Idx = getIdx(getSpillSize(DestReg));
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addFrameReference(BuildMI(MBB, MI, Opcode[Idx], 4, DestReg), FrameIdx);
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}
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void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
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@ -81,7 +78,7 @@ void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
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const TargetRegisterClass *RC) const {
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static const unsigned Opcode[] =
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{ X86::MOV8rr, X86::MOV16rr, X86::MOV32rr, X86::FpMOV };
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MBB.insert(MI, BuildMI(Opcode[getIdx(RC)],1,DestReg).addReg(SrcReg));
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BuildMI(MBB, MI, Opcode[getIdx(RC->getSize()*8)], 1, DestReg).addReg(SrcReg);
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}
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static MachineInstr *MakeMInst(unsigned Opcode, unsigned FrameIndex,
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