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https://github.com/c64scene-ar/llvm-6502.git
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R600/SI: simplify and fix SMRD encoding
The _SGPR variants where wrong. Patch by: Christian König Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174653 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -38,10 +38,6 @@ public:
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unsigned OpNo) const {
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return 0;
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}
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virtual uint32_t SMRDmemriEncode(const MachineInstr &MI, unsigned OpNo)
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const {
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return 0;
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}
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};
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} // End namespace llvm
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@ -72,8 +72,6 @@ private:
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bool SelectGlobalValueConstantOffset(SDValue Addr, SDValue& IntPtr);
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bool SelectGlobalValueVariableOffset(SDValue Addr,
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SDValue &BaseReg, SDValue& Offset);
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bool SelectADDR8BitOffset(SDValue Addr, SDValue& Base, SDValue& Offset);
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bool SelectADDRReg(SDValue Addr, SDValue& Base, SDValue& Offset);
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bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base, SDValue &Offset);
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bool SelectADDRIndirect(SDValue Addr, SDValue &Base, SDValue &Offset);
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@ -527,43 +525,6 @@ bool AMDGPUDAGToDAGISel::SelectGlobalValueVariableOffset(SDValue Addr,
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return false;
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}
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bool AMDGPUDAGToDAGISel::SelectADDR8BitOffset(SDValue Addr, SDValue& Base,
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SDValue& Offset) {
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if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress) {
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return false;
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}
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if (Addr.getOpcode() == ISD::ADD) {
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bool Match = false;
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// Find the base ptr and the offset
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for (unsigned i = 0; i < Addr.getNumOperands(); i++) {
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SDValue Arg = Addr.getOperand(i);
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ConstantSDNode * OffsetNode = dyn_cast<ConstantSDNode>(Arg);
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// This arg isn't a constant so it must be the base PTR.
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if (!OffsetNode) {
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Base = Addr.getOperand(i);
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continue;
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}
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// Check if the constant argument fits in 8-bits. The offset is in bytes
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// so we need to convert it to dwords.
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if (isUInt<8>(OffsetNode->getZExtValue() >> 2)) {
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Match = true;
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Offset = CurDAG->getTargetConstant(OffsetNode->getZExtValue() >> 2,
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MVT::i32);
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}
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}
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return Match;
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}
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// Default case, no offset
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Base = Addr;
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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}
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bool AMDGPUDAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
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SDValue &Offset) {
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ConstantSDNode * IMMOffset;
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@ -591,20 +552,6 @@ bool AMDGPUDAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
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return true;
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}
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bool AMDGPUDAGToDAGISel::SelectADDRReg(SDValue Addr, SDValue& Base,
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SDValue& Offset) {
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if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress ||
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Addr.getOpcode() != ISD::ADD) {
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return false;
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}
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Base = Addr.getOperand(0);
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Offset = Addr.getOperand(1);
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return true;
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}
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bool AMDGPUDAGToDAGISel::SelectADDRIndirect(SDValue Addr, SDValue &Base,
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SDValue &Offset) {
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ConstantSDNode *C;
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@ -49,10 +49,6 @@ public:
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SmallVectorImpl<MCFixup> &Fixups) const {
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return 0;
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}
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virtual uint32_t SMRDmemriEncode(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const {
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return 0;
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}
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};
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} // End namespace llvm
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@ -92,10 +92,6 @@ public:
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virtual unsigned GPR4AlignEncode(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixup) const;
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/// \brief Encoding for SMRD indexed loads
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virtual uint32_t SMRDmemriEncode(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixup) const;
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/// \brief Post-Encoder method for VOP instructions
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virtual uint64_t VOPPostEncode(const MCInst &MI, uint64_t Value) const;
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@ -183,36 +179,6 @@ unsigned SIMCCodeEmitter::GPR4AlignEncode(const MCInst &MI,
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return GPRAlign(MI, OpNo, 2);
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}
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#define SMRD_OFFSET_MASK 0xff
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#define SMRD_IMM_SHIFT 8
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#define SMRD_SBASE_MASK 0x3f
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#define SMRD_SBASE_SHIFT 9
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/// This function is responsibe for encoding the offset
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/// and the base ptr for SMRD instructions it should return a bit string in
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/// this format:
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///
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/// OFFSET = bits{7-0}
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/// IMM = bits{8}
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/// SBASE = bits{14-9}
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///
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uint32_t SIMCCodeEmitter::SMRDmemriEncode(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixup) const {
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uint32_t Encoding;
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const MCOperand &OffsetOp = MI.getOperand(OpNo + 1);
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//XXX: Use this function for SMRD loads with register offsets
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assert(OffsetOp.isImm());
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Encoding =
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(getMachineOpValue(MI, OffsetOp, Fixup) & SMRD_OFFSET_MASK)
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| (1 << SMRD_IMM_SHIFT) //XXX If the Offset is a register we shouldn't set this bit
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| ((GPR2AlignEncode(MI, OpNo, Fixup) & SMRD_SBASE_MASK) << SMRD_SBASE_SHIFT)
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;
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return Encoding;
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}
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//===----------------------------------------------------------------------===//
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// Post Encoder Callbacks
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//===----------------------------------------------------------------------===//
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@ -38,6 +38,11 @@ def SIvcc_bitcast : SDNode<"SIISD::VCC_BITCAST",
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SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>]>
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>;
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// SMRD takes a 64bit memory address and can only add an 32bit offset
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def SIadd64bit32bit : SDNode<"ISD::ADD",
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SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, SDTCisVT<0, i64>, SDTCisVT<2, i32>]>
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>;
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// Transformation function, extract the lower 32bit of a 64bit immediate
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def LO32 : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(N->getZExtValue() & 0xffffffff, MVT::i32);
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@ -48,6 +53,20 @@ def HI32 : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(N->getZExtValue() >> 32, MVT::i32);
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}]>;
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def IMM8bitDWORD : ImmLeaf <
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i32, [{
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return (Imm & ~0x3FC) == 0;
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}], SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(
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N->getZExtValue() >> 2, MVT::i32);
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}]>
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>;
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def IMM12bit : ImmLeaf <
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i16,
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[{return isUInt<12>(Imm);}]
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>;
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class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
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AMDGPUInst<outs, ins, asm, pattern> {
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@ -79,49 +98,16 @@ class SIOperand <ValueType vt, dag opInfo>: Operand <vt> {
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let MIOperandInfo = opInfo;
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}
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def IMM16bit : ImmLeaf <
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i16,
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[{return isInt<16>(Imm);}]
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>;
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def IMM8bit : ImmLeaf <
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i32,
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[{return (int32_t)Imm >= 0 && (int32_t)Imm <= 0xff;}]
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>;
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def IMM12bit : ImmLeaf <
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i16,
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[{return (int16_t)Imm >= 0 && (int16_t)Imm <= 0xfff;}]
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>;
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def IMM32bitIn64bit : ImmLeaf <
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i64,
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[{return isInt<32>(Imm);}]
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>;
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class GPR4Align <RegisterClass rc> : Operand <vAny> {
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let EncoderMethod = "GPR4AlignEncode";
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let MIOperandInfo = (ops rc:$reg);
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}
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class GPR2Align <RegisterClass rc, ValueType vt> : Operand <vt> {
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class GPR2Align <RegisterClass rc> : Operand <iPTR> {
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let EncoderMethod = "GPR2AlignEncode";
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let MIOperandInfo = (ops rc:$reg);
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}
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def SMRDmemrr : Operand<iPTR> {
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let MIOperandInfo = (ops SReg_64, SReg_32);
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let EncoderMethod = "GPR2AlignEncode";
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}
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def SMRDmemri : Operand<iPTR> {
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let MIOperandInfo = (ops SReg_64, i32imm);
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let EncoderMethod = "SMRDmemriEncode";
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}
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def ADDR_Reg : ComplexPattern<i64, 2, "SelectADDRReg", [], []>;
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def ADDR_Offset8 : ComplexPattern<i64, 2, "SelectADDR8BitOffset", [], []>;
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let Uses = [EXEC] in {
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def EXP : Enc64<
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@ -272,17 +258,15 @@ class MUBUF <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
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} // End Uses = [EXEC]
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class SMRD <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> :
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Enc32<outs, ins, asm, pattern> {
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class SMRD <bits<5> op, bits<1> imm, dag outs, dag ins, string asm,
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list<dag> pattern> : Enc32<outs, ins, asm, pattern> {
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bits<7> SDST;
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bits<15> PTR;
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bits<8> OFFSET = PTR{7-0};
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bits<1> IMM = PTR{8};
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bits<6> SBASE = PTR{14-9};
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bits<6> SBASE;
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bits<8> OFFSET;
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let Inst{7-0} = OFFSET;
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let Inst{8} = IMM;
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let Inst{8} = imm;
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let Inst{14-9} = SBASE;
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let Inst{21-15} = SDST;
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let Inst{26-22} = op;
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@ -573,29 +557,23 @@ class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBU
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let mayLoad = 0;
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}
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multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass dstClass,
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ValueType vt> {
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multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass dstClass> {
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def _IMM : SMRD <
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op,
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(outs dstClass:$dst),
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(ins SMRDmemri:$src0),
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asm,
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[(set (vt dstClass:$dst), (constant_load ADDR_Offset8:$src0))]
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op, 1,
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(outs dstClass:$dst),
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(ins GPR2Align<SReg_64>:$sbase, i32imm:$offset),
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asm,
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[]
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>;
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def _SGPR : SMRD <
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op,
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op, 0,
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(outs dstClass:$dst),
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(ins SMRDmemrr:$src0),
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(ins GPR2Align<SReg_64>:$sbase, SReg_32:$soff),
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asm,
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[(set (vt dstClass:$dst), (constant_load ADDR_Reg:$src0))]
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[]
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>;
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}
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multiclass SMRD_32 <bits<5> op, string asm, RegisterClass dstClass> {
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defm _F32 : SMRD_Helper <op, asm, dstClass, f32>;
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defm _I32 : SMRD_Helper <op, asm, dstClass, i32>;
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}
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include "SIInstrFormats.td"
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include "SIInstructions.td"
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@ -461,11 +461,13 @@ def TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Load_Helper <0x00000003, "TBUFFER_LOAD_FORM
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//def TBUFFER_STORE_FORMAT_XYZ : MTBUF_ <0x00000006, "TBUFFER_STORE_FORMAT_XYZ", []>;
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//def TBUFFER_STORE_FORMAT_XYZW : MTBUF_ <0x00000007, "TBUFFER_STORE_FORMAT_XYZW", []>;
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defm S_LOAD_DWORD : SMRD_32 <0x00000000, "S_LOAD_DWORD", SReg_32>;
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let mayLoad = 1 in {
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defm S_LOAD_DWORD : SMRD_Helper <0x00000000, "S_LOAD_DWORD", SReg_32>;
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//def S_LOAD_DWORDX2 : SMRD_DWORDX2 <0x00000001, "S_LOAD_DWORDX2", []>;
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defm S_LOAD_DWORDX4 : SMRD_Helper <0x00000002, "S_LOAD_DWORDX4", SReg_128, v4i32>;
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defm S_LOAD_DWORDX8 : SMRD_Helper <0x00000003, "S_LOAD_DWORDX8", SReg_256, v8i32>;
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defm S_LOAD_DWORDX4 : SMRD_Helper <0x00000002, "S_LOAD_DWORDX4", SReg_128>;
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defm S_LOAD_DWORDX8 : SMRD_Helper <0x00000003, "S_LOAD_DWORDX8", SReg_256>;
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//def S_LOAD_DWORDX16 : SMRD_DWORDX16 <0x00000004, "S_LOAD_DWORDX16", []>;
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//def S_BUFFER_LOAD_DWORD : SMRD_ <0x00000008, "S_BUFFER_LOAD_DWORD", []>;
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//def S_BUFFER_LOAD_DWORDX2 : SMRD_DWORDX2 <0x00000009, "S_BUFFER_LOAD_DWORDX2", []>;
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@ -473,6 +475,8 @@ defm S_LOAD_DWORDX8 : SMRD_Helper <0x00000003, "S_LOAD_DWORDX8", SReg_256, v8i32
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//def S_BUFFER_LOAD_DWORDX8 : SMRD_DWORDX8 <0x0000000b, "S_BUFFER_LOAD_DWORDX8", []>;
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//def S_BUFFER_LOAD_DWORDX16 : SMRD_DWORDX16 <0x0000000c, "S_BUFFER_LOAD_DWORDX16", []>;
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} // mayLoad = 1
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//def S_MEMTIME : SMRD_ <0x0000001e, "S_MEMTIME", []>;
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//def S_DCACHE_INV : SMRD_ <0x0000001f, "S_DCACHE_INV", []>;
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//def IMAGE_LOAD : MIMG_NoPattern_ <"IMAGE_LOAD", 0x00000000>;
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@ -1419,4 +1423,33 @@ def : Pat <(f32 (IL_mad AllReg_32:$src0, VReg_32:$src1, VReg_32:$src2)),
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(V_MAD_LEGACY_F32 AllReg_32:$src0, VReg_32:$src1, VReg_32:$src2,
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0, 0, 0, 0)>;
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/********** ================== **********/
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/********** SMRD Patterns **********/
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/********** ================== **********/
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multiclass SMRD_Pattern <SMRD Instr_IMM, SMRD Instr_SGPR, ValueType vt> {
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// 1. Offset as 8bit DWORD immediate
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def : Pat <
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(constant_load (SIadd64bit32bit SReg_64:$sbase, IMM8bitDWORD:$offset)),
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(vt (Instr_IMM SReg_64:$sbase, IMM8bitDWORD:$offset))
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>;
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// 2. Offset loaded in an 32bit SGPR
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def : Pat <
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(constant_load (SIadd64bit32bit SReg_64:$sbase, imm:$offset)),
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(vt (Instr_SGPR SReg_64:$sbase, (S_MOV_IMM_I32 imm:$offset)))
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>;
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// 3. No offset at all
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def : Pat <
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(constant_load SReg_64:$sbase),
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(vt (Instr_IMM SReg_64:$sbase, 0))
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>;
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}
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defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, f32>;
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defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, i32>;
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defm : SMRD_Pattern <S_LOAD_DWORDX4_IMM, S_LOAD_DWORDX4_SGPR, v4i32>;
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defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v8i32>;
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} // End isSI predicate
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