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Update comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59836 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -50,14 +50,14 @@ void ScheduleDAGInstrs::BuildSchedUnits() {
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assert(TRI->isPhysicalRegister(Reg) && "Virtual register encountered!");
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std::vector<SUnit *> &UseList = Uses[Reg];
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SUnit *&Def = Defs[Reg];
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// Optionally add output and anti dependences.
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// Optionally add output and anti dependencies.
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if (Def && Def != SU)
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Def->addPred(SU, /*isCtrl=*/true, /*isSpecial=*/false,
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Def->addPred(SU, /*isCtrl=*/true, /*isArtificial=*/false,
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/*PhyReg=*/Reg, Cost, /*isAntiDep=*/MO.isUse());
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for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
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SUnit *&Def = Defs[*Alias];
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if (Def && Def != SU)
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Def->addPred(SU, /*isCtrl=*/true, /*isSpecial=*/false,
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Def->addPred(SU, /*isCtrl=*/true, /*isArtificial=*/false,
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/*PhyReg=*/*Alias, Cost);
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}
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@ -65,13 +65,13 @@ void ScheduleDAGInstrs::BuildSchedUnits() {
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// Add any data dependencies.
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for (unsigned i = 0, e = UseList.size(); i != e; ++i)
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if (UseList[i] != SU)
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UseList[i]->addPred(SU, /*isCtrl=*/false, /*isSpecial=*/false,
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UseList[i]->addPred(SU, /*isCtrl=*/false, /*isArtificial=*/false,
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/*PhysReg=*/Reg, Cost);
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for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
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std::vector<SUnit *> &UseList = Uses[*Alias];
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for (unsigned i = 0, e = UseList.size(); i != e; ++i)
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if (UseList[i] != SU)
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UseList[i]->addPred(SU, /*isCtrl=*/false, /*isSpecial=*/false,
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UseList[i]->addPred(SU, /*isCtrl=*/false, /*isArtificial=*/false,
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/*PhysReg=*/*Alias, Cost);
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}
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@ -85,18 +85,18 @@ void ScheduleDAGInstrs::BuildSchedUnits() {
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bool True = true;
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if (!MI->isSafeToMove(TII, False)) {
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if (Chain)
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Chain->addPred(SU, /*isCtrl=*/false, /*isSpecial=*/false);
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Chain->addPred(SU, /*isCtrl=*/false, /*isArtificial=*/false);
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for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
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PendingLoads[k]->addPred(SU, /*isCtrl=*/false, /*isSpecial=*/false);
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PendingLoads[k]->addPred(SU, /*isCtrl=*/false, /*isArtificial=*/false);
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PendingLoads.clear();
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Chain = SU;
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} else if (!MI->isSafeToMove(TII, True)) {
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if (Chain)
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Chain->addPred(SU, /*isCtrl=*/false, /*isSpecial=*/false);
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Chain->addPred(SU, /*isCtrl=*/false, /*isArtificial=*/false);
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PendingLoads.push_back(SU);
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}
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if (Terminator && SU->Succs.empty())
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Terminator->addPred(SU, /*isCtrl=*/false, /*isSpecial=*/false);
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Terminator->addPred(SU, /*isCtrl=*/false, /*isArtificial=*/false);
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if (MI->getDesc().isTerminator() || MI->isLabel())
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Terminator = SU;
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