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Add AVX movmsk 256-bit intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110648 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1491,20 +1491,18 @@ let isAsmParserOnly = 1 in {
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defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
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"movmskpd", SSEPackedDouble>, OpSize,
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VEX;
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defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
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"movmskps", SSEPackedSingle>, VEX;
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defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
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"movmskpd", SSEPackedDouble>, OpSize,
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VEX;
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// FIXME: merge with multiclass above when the intrinsics come.
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// Assembler Only
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def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
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"movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
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def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
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"movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
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VEX;
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def VMOVMSKPSYrr : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR256:$src),
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"movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
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def VMOVMSKPDYrr : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR256:$src),
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"movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
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VEX;
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def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
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"movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
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def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
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