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We don't need to custom-select VLDMQ and VSTMQ anymore.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112336 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2010-08-28 00:20:11 +00:00
parent 6cfabc7974
commit fd7fd940c3
2 changed files with 7 additions and 42 deletions
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39
lib/Target/ARM/ARMISelDAGToDAG.cpp
View File

@ -481,7 +481,7 @@ bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N,
bool ARMDAGToDAGISel::SelectAddrMode4(SDNode *Op, SDValue N,
SDValue &Addr, SDValue &Mode) {
Addr = N;
Mode = CurDAG->getTargetConstant(0, MVT::i32);
Mode = CurDAG->getTargetConstant(ARM_AM::getAM4ModeImm(ARM_AM::ia), MVT::i32);
return true;
}
@ -2051,43 +2051,6 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
ResNode = SelectARMIndexedLoad(N);
if (ResNode)
return ResNode;
// VLDMQ must be custom-selected for "v2f64 load" to set the AM4 value.
if (Subtarget->hasVFP2() &&
N->getValueType(0).getSimpleVT().SimpleTy == MVT::v2f64) {
SDValue Chain = N->getOperand(0);
SDValue AM4Imm =
CurDAG->getTargetConstant(ARM_AM::getAM4ModeImm(ARM_AM::ia), MVT::i32);
SDValue Pred = getAL(CurDAG);
SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
SDValue Ops[] = { N->getOperand(1), AM4Imm, Pred, PredReg, Chain };
MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
MemOp[0] = cast<MemSDNode>(N)->getMemOperand();
SDNode *Ret = CurDAG->getMachineNode(ARM::VLDMQ, dl,
MVT::v2f64, MVT::Other, Ops, 5);
cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
return Ret;
}
// Other cases are autogenerated.
break;
}
case ISD::STORE: {
// VSTMQ must be custom-selected for "v2f64 store" to set the AM4 value.
if (Subtarget->hasVFP2() &&
N->getOperand(1).getValueType().getSimpleVT().SimpleTy == MVT::v2f64) {
SDValue Chain = N->getOperand(0);
SDValue AM4Imm =
CurDAG->getTargetConstant(ARM_AM::getAM4ModeImm(ARM_AM::ia), MVT::i32);
SDValue Pred = getAL(CurDAG);
SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
SDValue Ops[] = { N->getOperand(1), N->getOperand(2),
AM4Imm, Pred, PredReg, Chain };
MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
MemOp[0] = cast<MemSDNode>(N)->getMemOperand();
SDNode *Ret = CurDAG->getMachineNode(ARM::VSTMQ, dl, MVT::Other, Ops, 6);
cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
return Ret;
}
// Other cases are autogenerated.
break;
}

10
lib/Target/ARM/ARMInstrNEON.td
View File

@ -124,15 +124,16 @@ def nModImm : Operand<i32> {
// NEON load / store instructions
//===----------------------------------------------------------------------===//
let mayLoad = 1, neverHasSideEffects = 1 in {
// Use vldmia to load a Q register as a D register pair.
// This is equivalent to VLDMD except that it has a Q register operand
// instead of a pair of D registers.
def VLDMQ
: AXDI5<(outs QPR:$dst), (ins addrmode4:$addr, pred:$p),
IndexModeNone, IIC_fpLoadm,
"vldm${addr:submode}${p}\t$addr, ${dst:dregpair}", "", []>;
"vldm${addr:submode}${p}\t$addr, ${dst:dregpair}", "",
[(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]>;
let mayLoad = 1, neverHasSideEffects = 1 in {
// Use vld1 to load a Q register as a D register pair.
// This alternative to VLDMQ allows an alignment to be specified.
// This is equivalent to VLD1q64 except that it has a Q register operand.
@ -141,15 +142,16 @@ def VLD1q
IIC_VLD1, "vld1", "64", "${dst:dregpair}, $addr", "", []>;
} // mayLoad = 1, neverHasSideEffects = 1
let mayStore = 1, neverHasSideEffects = 1 in {
// Use vstmia to store a Q register as a D register pair.
// This is equivalent to VSTMD except that it has a Q register operand
// instead of a pair of D registers.
def VSTMQ
: AXDI5<(outs), (ins QPR:$src, addrmode4:$addr, pred:$p),
IndexModeNone, IIC_fpStorem,
"vstm${addr:submode}${p}\t$addr, ${src:dregpair}", "", []>;
"vstm${addr:submode}${p}\t$addr, ${src:dregpair}", "",
[(store (v2f64 QPR:$src), addrmode4:$addr)]>;
let mayStore = 1, neverHasSideEffects = 1 in {
// Use vst1 to store a Q register as a D register pair.
// This alternative to VSTMQ allows an alignment to be specified.
// This is equivalent to VST1q64 except that it has a Q register operand.