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Simplify and clean up some machine operand/instr printing/dumping stuff.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45456 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2007-12-30 21:01:27 +00:00
parent 0974d9a524
commit fde5f801be
1 changed files with 9 additions and 9 deletions
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18
lib/CodeGen/MachineInstr.cpp
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@ -267,15 +267,16 @@ void MachineInstr::dump() const {
cerr << " " << *this; cerr << " " << *this;
} }
static inline void OutputReg(std::ostream &os, unsigned RegNo, static void OutputReg(std::ostream &os, unsigned RegNo,
const MRegisterInfo *MRI = 0) { const MRegisterInfo *MRI = 0) {
if (!RegNo || MRegisterInfo::isPhysicalRegister(RegNo)) { if (MRegisterInfo::isPhysicalRegister(RegNo)) {
if (MRI) if (MRI)
os << "%" << MRI->get(RegNo).Name; os << "%" << MRI->get(RegNo).Name;
else else
os << "%mreg(" << RegNo << ")"; os << "%mreg" << RegNo;
} else } else {
os << "%reg" << RegNo; os << "%reg" << RegNo;
}
} }
static void print(const MachineOperand &MO, std::ostream &OS, static void print(const MachineOperand &MO, std::ostream &OS,
@ -287,6 +288,7 @@ static void print(const MachineOperand &MO, std::ostream &OS,
switch (MO.getType()) { switch (MO.getType()) {
case MachineOperand::MO_Register: case MachineOperand::MO_Register:
OutputReg(OS, MO.getReg(), MRI); OutputReg(OS, MO.getReg(), MRI);
if (MO.isDef()) OS << "<d>";
break; break;
case MachineOperand::MO_Immediate: case MachineOperand::MO_Immediate:
OS << MO.getImm(); OS << MO.getImm();
@ -384,11 +386,8 @@ void MachineInstr::print(std::ostream &os) const {
// and such. // and such.
os << getInstrDescriptor()->Name; os << getInstrDescriptor()->Name;
for (unsigned i = 0, N = getNumOperands(); i < N; i++) { for (unsigned i = 0, N = getNumOperands(); i < N; i++)
os << "\t" << getOperand(i); os << "\t" << getOperand(i);
if (getOperand(i).isRegister() && getOperand(i).isDef())
os << "<d>";
}
os << "\n"; os << "\n";
} }
@ -397,6 +396,7 @@ void MachineOperand::print(std::ostream &OS) const {
switch (getType()) { switch (getType()) {
case MO_Register: case MO_Register:
OutputReg(OS, getReg()); OutputReg(OS, getReg());
if (isDef()) OS << "<d>";
break; break;
case MO_Immediate: case MO_Immediate:
OS << getImm(); OS << getImm();