6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-04-03 18:32:50 +00:00
Code Issues Projects Releases Wiki Activity

Rejected 169195. As Duncan commented, bitcasting to proper type is wrong approach. We need to insert some valid TRANCATE node here.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162354 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Stepan Dyatkovskiy 2012-08-22 09:33:55 +00:00
parent 96601ca332
commit fdeb9fe5e0
2 changed files with 3 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -7876,29 +7876,9 @@ SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
if (VecIn1.getValueType().getSizeInBits()*2 != VT.getSizeInBits())
return SDValue();
// If the element type of the input vector is not the same as
// the output element type, make concat_vectors based on input element
// type and then bitcast it to the output vector type.
//
// In another words avoid nodes like this:
// <NODE> v16i8 = concat_vectors v4i16 v4i16
// Replace it with this one:
// <NODE0> v8i16 = concat_vectors v4i16 v4i16
// <NODE1> v16i8 = bitcast NODE0
EVT ItemType = VecIn1.getValueType().getVectorElementType();
if (ItemType != VT.getVectorElementType()) {
EVT ConcatVT = EVT::getVectorVT(*DAG.getContext(),
ItemType,
VecIn1.getValueType().getVectorNumElements()*2);
// Widen the input vector by adding undef values.
VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, ConcatVT,
VecIn1, DAG.getUNDEF(VecIn1.getValueType()));
VecIn1 = DAG.getNode(ISD::BITCAST, dl, VT, VecIn1);
} else
// Widen the input vector by adding undef values.
VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
VecIn1, DAG.getUNDEF(VecIn1.getValueType()));
// Widen the input vector by adding undef values.
VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT,
VecIn1, DAG.getUNDEF(VecIn1.getValueType()));
}
// If VecIn2 is unused then change it to undef.

10
test/CodeGen/ARM/crash-shufflevector.ll
View File

@ -1,10 +0,0 @@
; RUN: llc < %s -mtriple=armv7--
declare void @g(<16 x i8>)
define void @f(<4 x i8> %param1, <4 x i8> %param2) {
%y1 = shufflevector <4 x i8> %param1, <4 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%y2 = shufflevector <4 x i8> %param2, <4 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%z = shufflevector <16 x i8> %y1, <16 x i8> %y2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 18, i32 19>
call void @g(<16 x i8> %z)
ret void
}