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https://github.com/c64scene-ar/llvm-6502.git
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Pull utility routines with no SelectionDAG dependence out of
SelectionDAGBuilder. FunctionLoweringInfo isn't an ideal place for them to live, but it's better than SelectionDAGBuilder for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101267 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -369,3 +369,79 @@ void llvm::CopyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
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#endif
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}
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}
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/// hasInlineAsmMemConstraint - Return true if the inline asm instruction being
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/// processed uses a memory 'm' constraint.
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bool
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llvm::hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos,
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const TargetLowering &TLI) {
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for (unsigned i = 0, e = CInfos.size(); i != e; ++i) {
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InlineAsm::ConstraintInfo &CI = CInfos[i];
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for (unsigned j = 0, ee = CI.Codes.size(); j != ee; ++j) {
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TargetLowering::ConstraintType CType = TLI.getConstraintType(CI.Codes[j]);
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if (CType == TargetLowering::C_Memory)
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return true;
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}
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// Indirect operand accesses access memory.
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if (CI.isIndirect)
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return true;
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}
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return false;
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}
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/// getFCmpCondCode - Return the ISD condition code corresponding to
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/// the given LLVM IR floating-point condition code. This includes
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/// consideration of global floating-point math flags.
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///
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ISD::CondCode llvm::getFCmpCondCode(FCmpInst::Predicate Pred) {
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ISD::CondCode FPC, FOC;
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switch (Pred) {
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case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
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case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
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case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
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case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
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case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
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case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
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case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
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case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
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case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
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case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
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case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
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case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
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case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
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case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
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case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
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case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
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default:
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llvm_unreachable("Invalid FCmp predicate opcode!");
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FOC = FPC = ISD::SETFALSE;
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break;
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}
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if (FiniteOnlyFPMath())
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return FOC;
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else
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return FPC;
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}
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/// getICmpCondCode - Return the ISD condition code corresponding to
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/// the given LLVM IR integer condition code.
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///
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ISD::CondCode llvm::getICmpCondCode(ICmpInst::Predicate Pred) {
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switch (Pred) {
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case ICmpInst::ICMP_EQ: return ISD::SETEQ;
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case ICmpInst::ICMP_NE: return ISD::SETNE;
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case ICmpInst::ICMP_SLE: return ISD::SETLE;
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case ICmpInst::ICMP_ULE: return ISD::SETULE;
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case ICmpInst::ICMP_SGE: return ISD::SETGE;
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case ICmpInst::ICMP_UGE: return ISD::SETUGE;
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case ICmpInst::ICMP_SLT: return ISD::SETLT;
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case ICmpInst::ICMP_ULT: return ISD::SETULT;
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case ICmpInst::ICMP_SGT: return ISD::SETGT;
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case ICmpInst::ICMP_UGT: return ISD::SETUGT;
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default:
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llvm_unreachable("Invalid ICmp predicate opcode!");
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return ISD::SETNE;
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}
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}
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@ -15,12 +15,15 @@
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#ifndef FUNCTIONLOWERINGINFO_H
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#define FUNCTIONLOWERINGINFO_H
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#include "llvm/InlineAsm.h"
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#include "llvm/Instructions.h"
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#include "llvm/ADT/APInt.h"
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#include "llvm/ADT/DenseMap.h"
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#ifndef NDEBUG
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#include "llvm/ADT/SmallSet.h"
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#endif
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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#include <vector>
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namespace llvm {
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@ -146,6 +149,22 @@ void AddCatchInfo(CallInst &I, MachineModuleInfo *MMI, MachineBasicBlock *MBB);
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void CopyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
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MachineModuleInfo *MMI, FunctionLoweringInfo &FLI);
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/// hasInlineAsmMemConstraint - Return true if the inline asm instruction being
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/// processed uses a memory 'm' constraint.
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bool hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos,
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const TargetLowering &TLI);
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/// getFCmpCondCode - Return the ISD condition code corresponding to
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/// the given LLVM IR floating-point condition code. This includes
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/// consideration of global floating-point math flags.
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///
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ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred);
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/// getICmpCondCode - Return the ISD condition code corresponding to
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/// the given LLVM IR integer condition code.
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///
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ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred);
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} // end namespace llvm
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#endif
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@ -972,61 +972,6 @@ static bool InBlock(const Value *V, const BasicBlock *BB) {
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return true;
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}
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/// getFCmpCondCode - Return the ISD condition code corresponding to
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/// the given LLVM IR floating-point condition code. This includes
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/// consideration of global floating-point math flags.
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///
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static ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred) {
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ISD::CondCode FPC, FOC;
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switch (Pred) {
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case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
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case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
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case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
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case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
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case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
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case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
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case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
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case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
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case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
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case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
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case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
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case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
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case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
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case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
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case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
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case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
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default:
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llvm_unreachable("Invalid FCmp predicate opcode!");
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FOC = FPC = ISD::SETFALSE;
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break;
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}
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if (FiniteOnlyFPMath())
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return FOC;
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else
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return FPC;
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}
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/// getICmpCondCode - Return the ISD condition code corresponding to
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/// the given LLVM IR integer condition code.
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///
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static ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred) {
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switch (Pred) {
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case ICmpInst::ICMP_EQ: return ISD::SETEQ;
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case ICmpInst::ICMP_NE: return ISD::SETNE;
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case ICmpInst::ICMP_SLE: return ISD::SETLE;
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case ICmpInst::ICMP_ULE: return ISD::SETULE;
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case ICmpInst::ICMP_SGE: return ISD::SETGE;
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case ICmpInst::ICMP_UGE: return ISD::SETUGE;
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case ICmpInst::ICMP_SLT: return ISD::SETLT;
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case ICmpInst::ICMP_ULT: return ISD::SETULT;
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case ICmpInst::ICMP_SGT: return ISD::SETGT;
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case ICmpInst::ICMP_UGT: return ISD::SETUGT;
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default:
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llvm_unreachable("Invalid ICmp predicate opcode!");
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return ISD::SETNE;
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}
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}
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/// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
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/// This function emits a branch and is used at the leaves of an OR or an
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/// AND operator tree.
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@ -5213,27 +5158,6 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
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// Otherwise, we couldn't allocate enough registers for this.
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}
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/// hasInlineAsmMemConstraint - Return true if the inline asm instruction being
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/// processed uses a memory 'm' constraint.
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static bool
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hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos,
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const TargetLowering &TLI) {
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for (unsigned i = 0, e = CInfos.size(); i != e; ++i) {
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InlineAsm::ConstraintInfo &CI = CInfos[i];
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for (unsigned j = 0, ee = CI.Codes.size(); j != ee; ++j) {
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TargetLowering::ConstraintType CType = TLI.getConstraintType(CI.Codes[j]);
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if (CType == TargetLowering::C_Memory)
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return true;
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}
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// Indirect operand accesses access memory.
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if (CI.isIndirect)
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return true;
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}
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return false;
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}
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/// visitInlineAsm - Handle a call to an InlineAsm object.
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///
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void SelectionDAGBuilder::visitInlineAsm(CallSite CS) {
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