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Annotate X86InstrCMovSetCC.td with SchedRW lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177459 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -16,7 +16,7 @@
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// SetCC instructions.
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multiclass CMOV<bits<8> opc, string Mnemonic, PatLeaf CondNode> {
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let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst",
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isCommutable = 1 in {
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isCommutable = 1, SchedRW = [WriteALU] in {
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def NAME#16rr
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: I<opc, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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!strconcat(Mnemonic, "{w}\t{$src2, $dst|$dst, $src2}"),
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@ -37,7 +37,8 @@ multiclass CMOV<bits<8> opc, string Mnemonic, PatLeaf CondNode> {
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IIC_CMOV32_RR>, TB;
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}
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let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst" in {
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let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst",
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SchedRW = [WriteALULd, ReadAfterLd] in {
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def NAME#16rm
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: I<opc, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
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!strconcat(Mnemonic, "{w}\t{$src2, $dst|$dst, $src2}"),
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@ -83,11 +84,11 @@ multiclass SETCC<bits<8> opc, string Mnemonic, PatLeaf OpNode> {
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def r : I<opc, MRM0r, (outs GR8:$dst), (ins),
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!strconcat(Mnemonic, "\t$dst"),
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[(set GR8:$dst, (X86setcc OpNode, EFLAGS))],
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IIC_SET_R>, TB;
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IIC_SET_R>, TB, Sched<[WriteALU]>;
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def m : I<opc, MRM0m, (outs), (ins i8mem:$dst),
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!strconcat(Mnemonic, "\t$dst"),
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[(store (X86setcc OpNode, EFLAGS), addr:$dst)],
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IIC_SET_M>, TB;
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IIC_SET_M>, TB, Sched<[WriteALU, WriteStore]>;
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} // Uses = [EFLAGS]
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}
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