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In DelayForLiveRegsBottomUp, handle instructions that read and write

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the same physical register. Simplifies the fix from the previous
checkin r122211.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122370 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick 2010-12-21 22:27:44 +00:00
parent 38036d8b36
commit feac09801b
1 changed files with 4 additions and 15 deletions
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19
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
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@ -660,9 +660,12 @@ DelayForLiveRegsBottomUp(SUnit *SU, SmallVector<unsigned, 4> &LRegs) {
SmallSet<unsigned, 4> RegAdded; SmallSet<unsigned, 4> RegAdded;
// If this node would clobber any "live" register, then it's not ready. // If this node would clobber any "live" register, then it's not ready.
//
// If SU is the currently live definition of the same register that it uses,
// then we are free to schedule it.
for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
I != E; ++I) { I != E; ++I) {
if (I->isAssignedRegDep()) if (I->isAssignedRegDep() && LiveRegDefs[I->getReg()] != SU)
CheckForLiveRegDef(I->getSUnit(), I->getReg(), LiveRegDefs, CheckForLiveRegDef(I->getSUnit(), I->getReg(), LiveRegDefs,
RegAdded, LRegs, TRI); RegAdded, LRegs, TRI);
} }
@ -703,20 +706,6 @@ DelayForLiveRegsBottomUp(SUnit *SU, SmallVector<unsigned, 4> &LRegs) {
CheckForLiveRegDef(SU, *Reg, LiveRegDefs, RegAdded, LRegs, TRI); CheckForLiveRegDef(SU, *Reg, LiveRegDefs, RegAdded, LRegs, TRI);
} }
// Okay, we now know all of the live registers that are defined by an
// immediate predecessor. It is ok to kill these registers if we are also
// using it.
for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
I != E; ++I) {
if (I->isAssignedRegDep() &&
LiveRegCycles[I->getReg()] == I->getSUnit()->getHeight()) {
unsigned Reg = I->getReg();
if (RegAdded.erase(Reg))
LRegs.erase(std::find(LRegs.begin(), LRegs.end(), Reg));
}
}
return !LRegs.empty(); return !LRegs.empty();
} }