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https://github.com/c64scene-ar/llvm-6502.git
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Add codegen support for NEON vld3 intrinsics with 128-bit vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83471 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -444,7 +444,7 @@ bool ARMDAGToDAGISel::SelectAddrMode6(SDValue Op, SDValue N,
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SDValue &Addr, SDValue &Update,
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SDValue &Opc) {
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Addr = N;
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// The optional writeback is handled in ARMLoadStoreOpt.
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// Default to no writeback.
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Update = CurDAG->getRegister(0, MVT::i32);
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Opc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(false), MVT::i32);
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return true;
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@ -1388,6 +1388,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
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SDValue MemAddr, MemUpdate, MemOpc;
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if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
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return NULL;
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if (VT.is64BitVector()) {
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switch (VT.getSimpleVT().SimpleTy) {
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default: llvm_unreachable("unhandled vld3 type");
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case MVT::v8i8: Opc = ARM::VLD3d8; break;
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@ -1399,6 +1400,46 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
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const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
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return CurDAG->getMachineNode(Opc, dl, VT, VT, VT, MVT::Other, Ops, 4);
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}
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// Quad registers are loaded with two separate instructions, where one
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// loads the even registers and the other loads the odd registers.
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EVT RegVT = VT;
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unsigned Opc2 = 0;
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switch (VT.getSimpleVT().SimpleTy) {
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default: llvm_unreachable("unhandled vld3 type");
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case MVT::v16i8:
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Opc = ARM::VLD3q8a; Opc2 = ARM::VLD3q8b; RegVT = MVT::v8i8; break;
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case MVT::v8i16:
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Opc = ARM::VLD3q16a; Opc2 = ARM::VLD3q16b; RegVT = MVT::v4i16; break;
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case MVT::v4f32:
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Opc = ARM::VLD3q32a; Opc2 = ARM::VLD3q32b; RegVT = MVT::v2f32; break;
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case MVT::v4i32:
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Opc = ARM::VLD3q32a; Opc2 = ARM::VLD3q32b; RegVT = MVT::v2i32; break;
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}
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SDValue Chain = N->getOperand(0);
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// Enable writeback to the address register.
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MemOpc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(true), MVT::i32);
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std::vector<EVT> ResTys(3, RegVT);
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ResTys.push_back(MemAddr.getValueType());
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ResTys.push_back(MVT::Other);
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const SDValue OpsA[] = { MemAddr, MemUpdate, MemOpc, Chain };
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SDNode *VLdA = CurDAG->getMachineNode(Opc, dl, ResTys, OpsA, 4);
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Chain = SDValue(VLdA, 4);
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const SDValue OpsB[] = { SDValue(VLdA, 3), MemUpdate, MemOpc, Chain };
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SDNode *VLdB = CurDAG->getMachineNode(Opc2, dl, ResTys, OpsB, 4);
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Chain = SDValue(VLdB, 4);
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SDNode *Q0 = PairDRegs(VT, SDValue(VLdA, 0), SDValue(VLdB, 0));
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SDNode *Q1 = PairDRegs(VT, SDValue(VLdA, 1), SDValue(VLdB, 1));
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SDNode *Q2 = PairDRegs(VT, SDValue(VLdA, 2), SDValue(VLdB, 2));
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ReplaceUses(SDValue(N, 0), SDValue(Q0, 0));
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ReplaceUses(SDValue(N, 1), SDValue(Q1, 0));
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ReplaceUses(SDValue(N, 2), SDValue(Q2, 0));
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ReplaceUses(SDValue(N, 3), Chain);
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return NULL;
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}
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case Intrinsic::arm_neon_vld4: {
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SDValue MemAddr, MemUpdate, MemOpc;
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@ -201,11 +201,26 @@ class VLD3D<string OpcodeStr>
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: NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3), (ins addrmode6:$addr),
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IIC_VLD3,
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!strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3\\}, $addr"), "", []>;
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class VLD3WB<string OpcodeStr>
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: NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb),
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(ins addrmode6:$addr), IIC_VLD3,
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!strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3\\}, $addr"),
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"$addr.addr = $wb", []>;
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def VLD3d8 : VLD3D<"vld3.8">;
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def VLD3d16 : VLD3D<"vld3.16">;
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def VLD3d32 : VLD3D<"vld3.32">;
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// vld3 to double-spaced even registers.
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def VLD3q8a : VLD3WB<"vld3.8">;
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def VLD3q16a : VLD3WB<"vld3.16">;
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def VLD3q32a : VLD3WB<"vld3.32">;
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// vld3 to double-spaced odd registers.
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def VLD3q8b : VLD3WB<"vld3.8">;
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def VLD3q16b : VLD3WB<"vld3.16">;
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def VLD3q32b : VLD3WB<"vld3.32">;
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// VLD4 : Vector Load (multiple 4-element structures)
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class VLD4D<string OpcodeStr>
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: NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
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@ -36,8 +36,12 @@ namespace {
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char NEONPreAllocPass::ID = 0;
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}
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static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd,
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unsigned &NumRegs) {
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static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
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unsigned &Offset, unsigned &Stride) {
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// Default to unit stride with no offset.
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Stride = 1;
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Offset = 0;
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switch (Opcode) {
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default:
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break;
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@ -69,6 +73,24 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd,
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NumRegs = 3;
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return true;
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case ARM::VLD3q8a:
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case ARM::VLD3q16a:
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case ARM::VLD3q32a:
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FirstOpnd = 0;
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NumRegs = 3;
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Offset = 0;
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Stride = 2;
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return true;
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case ARM::VLD3q8b:
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case ARM::VLD3q16b:
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case ARM::VLD3q32b:
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FirstOpnd = 0;
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NumRegs = 3;
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Offset = 1;
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Stride = 2;
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return true;
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case ARM::VLD4d8:
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case ARM::VLD4d16:
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case ARM::VLD4d32:
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@ -149,8 +171,8 @@ bool NEONPreAllocPass::PreAllocNEONRegisters(MachineBasicBlock &MBB) {
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MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
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for (; MBBI != E; ++MBBI) {
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MachineInstr *MI = &*MBBI;
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unsigned FirstOpnd, NumRegs;
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if (!isNEONMultiRegOp(MI->getOpcode(), FirstOpnd, NumRegs))
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unsigned FirstOpnd, NumRegs, Offset, Stride;
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if (!isNEONMultiRegOp(MI->getOpcode(), FirstOpnd, NumRegs, Offset, Stride))
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continue;
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MachineBasicBlock::iterator NextI = next(MBBI);
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@ -164,9 +186,10 @@ bool NEONPreAllocPass::PreAllocNEONRegisters(MachineBasicBlock &MBB) {
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// For now, just assign a fixed set of adjacent registers.
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// This leaves plenty of room for future improvements.
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static const unsigned NEONDRegs[] = {
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ARM::D0, ARM::D1, ARM::D2, ARM::D3
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ARM::D0, ARM::D1, ARM::D2, ARM::D3,
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ARM::D4, ARM::D5, ARM::D6, ARM::D7
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};
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MO.setReg(NEONDRegs[R]);
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MO.setReg(NEONDRegs[Offset + R * Stride]);
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if (MO.isUse()) {
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// Insert a copy from VirtReg.
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@ -5,6 +5,11 @@
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%struct.__neon_int32x2x3_t = type { <2 x i32>, <2 x i32>, <2 x i32> }
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%struct.__neon_float32x2x3_t = type { <2 x float>, <2 x float>, <2 x float> }
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%struct.__neon_int8x16x3_t = type { <16 x i8>, <16 x i8>, <16 x i8> }
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%struct.__neon_int16x8x3_t = type { <8 x i16>, <8 x i16>, <8 x i16> }
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%struct.__neon_int32x4x3_t = type { <4 x i32>, <4 x i32>, <4 x i32> }
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%struct.__neon_float32x4x3_t = type { <4 x float>, <4 x float>, <4 x float> }
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define <8 x i8> @vld3i8(i8* %A) nounwind {
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;CHECK: vld3i8:
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;CHECK: vld3.8
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@ -45,7 +50,56 @@ define <2 x float> @vld3f(float* %A) nounwind {
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ret <2 x float> %tmp4
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}
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define <16 x i8> @vld3Qi8(i8* %A) nounwind {
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;CHECK: vld3Qi8:
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;CHECK: vld3.8
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;CHECK: vld3.8
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%tmp1 = call %struct.__neon_int8x16x3_t @llvm.arm.neon.vld3.v16i8(i8* %A)
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%tmp2 = extractvalue %struct.__neon_int8x16x3_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int8x16x3_t %tmp1, 2
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%tmp4 = add <16 x i8> %tmp2, %tmp3
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ret <16 x i8> %tmp4
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}
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define <8 x i16> @vld3Qi16(i16* %A) nounwind {
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;CHECK: vld3Qi16:
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;CHECK: vld3.16
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;CHECK: vld3.16
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%tmp1 = call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3.v8i16(i16* %A)
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%tmp2 = extractvalue %struct.__neon_int16x8x3_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int16x8x3_t %tmp1, 2
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%tmp4 = add <8 x i16> %tmp2, %tmp3
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ret <8 x i16> %tmp4
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}
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define <4 x i32> @vld3Qi32(i32* %A) nounwind {
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;CHECK: vld3Qi32:
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;CHECK: vld3.32
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;CHECK: vld3.32
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%tmp1 = call %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3.v4i32(i32* %A)
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%tmp2 = extractvalue %struct.__neon_int32x4x3_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_int32x4x3_t %tmp1, 2
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%tmp4 = add <4 x i32> %tmp2, %tmp3
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ret <4 x i32> %tmp4
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}
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define <4 x float> @vld3Qf(float* %A) nounwind {
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;CHECK: vld3Qf:
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;CHECK: vld3.32
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;CHECK: vld3.32
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%tmp1 = call %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3.v4f32(float* %A)
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%tmp2 = extractvalue %struct.__neon_float32x4x3_t %tmp1, 0
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%tmp3 = extractvalue %struct.__neon_float32x4x3_t %tmp1, 2
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%tmp4 = add <4 x float> %tmp2, %tmp3
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ret <4 x float> %tmp4
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}
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declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8*) nounwind readonly
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declare %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16(i8*) nounwind readonly
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declare %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3.v2i32(i8*) nounwind readonly
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declare %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3.v2f32(i8*) nounwind readonly
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declare %struct.__neon_int8x16x3_t @llvm.arm.neon.vld3.v16i8(i8*) nounwind readonly
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declare %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3.v8i16(i8*) nounwind readonly
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declare %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3.v4i32(i8*) nounwind readonly
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declare %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3.v4f32(i8*) nounwind readonly
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