Commit Graph

31219 Commits

Author SHA1 Message Date
Damián Silvani 0f0de95ee3 Define first regression test (copied from SPARC) 2015-08-03 20:15:00 -03:00
Simon Pilgrim 61147ebb94 [X86][SSE] Refreshed sse2 vector shift tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243850 91177308-0d34-0410-b5e6-96231b3b80d8
2015-08-02 15:23:53 +00:00
Jingyue Wu 6ebf387fdd [NVPTX] allow register copy between float and int
Summary:
Fixes PR24303. With Bruno's WIP (D11197) on PeepholeOptimizer, across-class
register copying (e.g. i32 to f32) becomes possible. Enhance
NVPTXInstrInfo::copyPhysReg to handle these cases.

Reviewers: jholewinski

Subscribers: eliben, jholewinski, llvm-commits, bruno

Differential Revision: http://reviews.llvm.org/D11622

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243839 91177308-0d34-0410-b5e6-96231b3b80d8
2015-08-01 18:02:12 +00:00
Simon Atanasyan e35d602838 [Mips] Support DT_MIPS_RLD_MAP_REL dynamic section tag in the llvm-readobj
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243833 91177308-0d34-0410-b5e6-96231b3b80d8
2015-08-01 12:02:02 +00:00
Simon Pilgrim fa2c240c15 [DAGCombiner] Convert constant AND masks to shuffle clear masks down to the byte level
The XformToShuffleWithZero method currently checks AND masks at the per-lane level for all-one and all-zero constants and attempts to convert them to legal shuffle clear masks.

This patch generalises XformToShuffleWithZero, splitting and checking the sub-lanes of the constants down to the byte level to see if any legal shuffle clear masks are possible. This allows a lot of masks (often from legalization or truncation) to be folded into existing shuffle patterns and removes a lot of constant mask loading.

There are a few examples of poor shuffle lowering that are exposed by this patch that will be cleaned up in future patches (e.g. merging shuffles that are separated by bitcasts, x86 legalized v8i8 zero extension uses PMOVZX+AND+AND instead of AND+PMOVZX, etc.)

Differential Revision: http://reviews.llvm.org/D11518

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243831 91177308-0d34-0410-b5e6-96231b3b80d8
2015-08-01 10:01:46 +00:00
JF Bastien e428ba798e WebAssembly: handle more than int32 argument/return
Summary: Also test 64-bit integers, except shifts for now which are broken because isel dislikes the 32-bit truncate that precedes them.

Reviewers: sunfish

Subscribers: llvm-commits, jfb

Differential Revision: http://reviews.llvm.org/D11699

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243822 91177308-0d34-0410-b5e6-96231b3b80d8
2015-08-01 04:48:44 +00:00
Alex Lorenz f5cf675376 AMDGPU/SI: Add implicit register operands in the correct order.
This commit fixes a bug in the class 'SIInstrInfo' where the implicit register
machine operands were added to a machine instruction in an incorrect order -
the implicit uses were added before the implicit defs.

I found this bug while working on moving the implicit register operand
verification code from the MIR parser to the machine verifier.

This commit also makes the method 'addImplicitDefUseOperands' in the machine
instruction class public so that it can be reused in the 'SIInstrInfo' class.

Reviewers: Matt Arsenault

Differential Revision: http://reviews.llvm.org/D11689


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243799 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 23:30:09 +00:00
Alex Lorenz c198b23a4d MIR Parser: Report an error when a jump table entry is redefined.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243798 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 23:13:23 +00:00
Jingyue Wu bd11ccb2b9 [NVPTX] convert pointers in byval kernel arguments to global
Summary:
For example, in

  struct S {
    int *x;
    int *y;
  };
  __global__ void foo(S s) {
    int *b = s.y;
    // use b
  }

"b" is guaranteed to point to global. NVPTX should emit ld.global/st.global for
accessing "b".

Reviewers: jholewinski

Subscribers: llvm-commits, jholewinski

Differential Revision: http://reviews.llvm.org/D11505

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243790 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 21:44:14 +00:00
JF Bastien caf175c28c WebAssembly: handle `ret void`.
Summary:
Use -1 as numoperands for the return SDTypeProfile, denoting that return is variadic. Note that the patterns in InstrControl.td still need to match the inputs, so this ins't an "anything goes" variadic on ret!

The next step will be to handle other local types (not just int32).

Reviewers: sunfish

Subscribers: llvm-commits, jfb

Differential Revision: http://reviews.llvm.org/D11692

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243783 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 21:04:18 +00:00
Alex Lorenz c225eda1f1 MIR Serialization: Serialize the floating point immediate machine operands.
Reviewers: Duncan P. N. Exon Smith


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243780 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 20:49:21 +00:00
Duncan P. N. Exon Smith 82e3e48d52 IR: Add a broad bitcode compatibility test
Successive versions of LLVM should retain the ability to parse bitcode
generated by old releases of the compiler.  This adds a bitcode format
compatibility test, which is intended to provide good (albeit not
entirely exhaustive) coverage of the current LangRef.

This also includes compatibility tests for LLVM 3.6.  After every 3.X.0
release, the compatibility.ll file from the 3.X branch should be copied
to compatibility-3.X.ll on trunk, and the 3.X.0 release used to generate
a corresponding bitcode file.

Patch by Vedant Kumar!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243779 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 20:44:32 +00:00
Frederic Riss 09e26a42d2 [dwarfdump] Ignore scattered relocations for mach-o.
When encountering a scattered relocation, the code would assert trying to
access an unexisting section. I couldn't find a way to expose the result
of the processing of a scattered reloc, and I'm really unsure what the
right thing to do is. This patch just skips them during the processing in
DwarfContext and adds a mach-o file to the tests that exposed the asserting
behavior.
(This is a new failure that is being exposed by Rafael's recent work on
the libObject interfaces. I think the wrong behavior has always happened,
but now it's asserting)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243778 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 20:22:50 +00:00
Frederic Riss d353c91d49 [dsymutil] Support multiple input files on the command line
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243777 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 20:22:20 +00:00
Duncan P. N. Exon Smith bf2040f00c DI: Remove DW_TAG_arg_variable and DW_TAG_auto_variable
Remove the fake `DW_TAG_auto_variable` and `DW_TAG_arg_variable` tags,
using `DW_TAG_variable` in their place Stop exposing the `tag:` field at
all in the assembly format for `DILocalVariable`.

Most of the testcase updates were generated by the following sed script:

    find test/ -name "*.ll" -o -name "*.mir" |
    xargs grep -l 'DILocalVariable' |
    xargs sed -i '' \
      -e 's/tag: DW_TAG_arg_variable, //' \
      -e 's/tag: DW_TAG_auto_variable, //'

There were only a handful of tests in `test/Assembly` that I needed to
update by hand.

(Note: a follow-up could change `DILocalVariable::DILocalVariable()` to
set the tag to `DW_TAG_formal_parameter` instead of `DW_TAG_variable`
(as appropriate), instead of having that logic magically in the backend
in `DbgVariable`.  I've added a FIXME to that effect.)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243774 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 18:58:39 +00:00
JF Bastien 6877df25a0 WebAssembly: handle unused function arguments.
Subscribers: llvm-commits, sunfish, jfb

Differential Revision: http://reviews.llvm.org/D11684

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243770 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 18:13:27 +00:00
David Majnemer 4a45f0871a New EH representation for MSVC compatibility
This introduces new instructions neccessary to implement MSVC-compatible
exception handling support.  Most of the middle-end and none of the
back-end haven't been audited or updated to take them into account.

Differential Revision: http://reviews.llvm.org/D11097

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243766 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 17:58:14 +00:00
JF Bastien 3f2cb5c959 WebAssembly: print basic integer assembly.
Summary:
This prints assembly for int32 integer operations defined in WebAssemblyInstrInteger.td only, with major caveats:

  - The operation names are currently incorrect.
  - Other integer and floating-point types will be added later.
  - The printer isn't factored out to handle recursive AST code yet, since it can't even handle control flow anyways.
  - The assembly format isn't full s-expressions yet either, this will be added later.
  - This currently disables PrologEpilogCodeInserter as well as MachineCopyPropagation becasue they don't like virtual registers, which WebAssembly likes quite a bit. This will be fixed by factoring out NVPTX's change (currently a fork of PrologEpilogCodeInserter).

Reviewers: sunfish

Subscribers: llvm-commits, jfb

Differential Revision: http://reviews.llvm.org/D11671

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243763 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 17:53:38 +00:00
Sanjay Patel 8ae0800ae1 [x86] reassociate integer multiplies using machine combiner pass
Add i16, i32, i64 imul machine instructions to the list of reassociation
candidates.

A new bit of logic is needed to handle integer instructions: they have an
implicit EFLAGS operand, so we have to make sure it's dead in order to do
any reassociation with integer ops.

Differential Revision: http://reviews.llvm.org/D11660



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243756 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 16:21:55 +00:00
Reid Kleckner c136e5507a [COFF] Return symbol VAs instead of RVAs for PE files
This makes llvm-nm consistent with binutils nm on executables and DLLs.
For a vanilla hello world executable, the address of main should include
the default image base of 0x400000.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243755 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 16:14:22 +00:00
Geoff Berry 0dd663b598 [AArch64] Favor extended reg patterns for sub
Summary:
Favor the extended reg patterns over the shifted reg patterns that match
only the operand shift and not the full sign/zero extend and shift.

Reviewers: jmolloy, t.p.northover

Subscribers: mcrosier, aemerson, llvm-commits, rengolin

Differential Revision: http://reviews.llvm.org/D11569

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243753 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 15:55:54 +00:00
Matt Arsenault 30eac4b85a AMDGPU: Fix v16i32 to v16i8 truncstore
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243731 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 04:12:04 +00:00
Kostya Serebryany 02c18f4db9 [libFuzzer] trace switch statements and apply mutations based on the expected case values
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243726 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 01:33:06 +00:00
Tom Stellard 8cb3db9e93 ELFYAML: Enable parsing of EM_AMDGPU
Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11263

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243724 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 01:15:15 +00:00
Matt Arsenault 6a224c30a5 TableGen: Support folding casts from bits to int
This is to fix an incorrect error when trying to initialize
DwarfNumbers with a !cast<int> of a bits initializer.
getValuesAsListOfInts("DwarfNumbers") would not see an IntInit
and instead the cast, so would give up.

It seems likely that this could be generalized to attempt
the convertInitializerTo for any type. I'm not really sure
why the existing code seems to special case the string cast cases
when convertInitializerTo seems like it should generally handle this
sort of thing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243722 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 01:12:06 +00:00
Sumanth Gundapaneni 8d13756ddd [ARM] Lower modulo operation to generate __aeabi_divmod on Android
For a modulo (reminder) operation,
clang -target armv7-none-linux-gnueabi generates "__modsi3"
clang -target armv7-none-eabi generates "__aeabi_idivmod"
clang -target armv7-linux-androideabi generates "__modsi3"
Android bionic libc doesn't provide a __modsi3, instead it provides a
"__aeabi_idivmod". This patch fixes the LLVM ARMISelLowering to generate
the correct call when ever there is a modulo operation.

Differential Revision: http://reviews.llvm.org/D11661


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243717 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 00:45:12 +00:00
Alex Lorenz 2623dd4454 MIR Parser: Report an error when a constant pool item is redefined.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243696 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-30 22:00:17 +00:00
Alex Lorenz 2bc631660b MIR Parser: Report an error when a virtual register is redefined.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243695 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-30 21:54:10 +00:00
Sanjay Patel 8a6197a968 fix memcpy/memset/memmove lowering when optimizing for size
Fixing MinSize attribute handling was discussed in D11363. 
This is a prerequisite patch to doing that.

The handling of OptSize when lowering mem* functions was broken
on Darwin because it wants to ignore -Os for these cases, but the
existing logic also made it ignore -Oz (MinSize).

The Linux change demonstrates a widespread problem. The backend
doesn't usually recognize the MinSize attribute by itself; it
assumes that if the MinSize attribute exists, then the OptSize 
attribute must also exist. 

Fixing this more generally will be a follow-on patch or two.

Differential Revision: http://reviews.llvm.org/D11568



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243693 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-30 21:41:50 +00:00
Wei Mi 4db6728b3a [SLP vectorizer]: Choose the best consecutive candidate to pair with a store instruction.
The patch changes the SLPVectorizer::vectorizeStores to choose the immediate
succeeding or preceding candidate for a store instruction when it has multiple
consecutive candidates. In this way it has better chance to find more slp
vectorization opportunities.

Differential Revision: http://reviews.llvm.org/D10445


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243666 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-30 17:40:39 +00:00
Alex Lorenz fbd94791e6 MIR Serialization: Serialize the machine basic block's successor weights.
Reviewers: Duncan P. N. Exon Smith


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243659 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-30 16:54:38 +00:00
Vasileios Kalintiris f04b7c7d06 [mips] Fix out-of-date debug information in test file.
Update the debug info in the check-lines because the change in r243638
introduced a constant initialization before the prologue's end as part
of a register spill.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243640 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-30 13:13:09 +00:00
Vasileios Kalintiris 458b5f3d9b [mips][FastISel] Remove hidden mips-fast-isel option.
Summary:
This hidden option would disable code generation through FastISel by
default. It was removed from the available options and from the
Fast-ISel tests that required it in order to run the tests.

Reviewers: dsanders

Subscribers: qcolombet, llvm-commits

Differential Revision: http://reviews.llvm.org/D11610

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243638 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-30 12:39:33 +00:00
Vasileios Kalintiris 3b79f0ccc3 [mips][FastISel] Apply only zero-extension to constants prior to their materialization.
Summary:
Previously, we would sign-extend non-boolean negative constants and
zero-extend otherwise. This was problematic for PHI instructions with
negative values that had a type with bitwidth less than that of the
register used for materialization.

More specifically, ComputePHILiveOutRegInfo() assumes the constants
present in a PHI node are zero extended in their container and
afterwards deduces the known bits.

For example, previously we would materialize an i16 -4 with the
following instruction:

  addiu $r, $zero, -4

The register would end-up with the 32-bit 2's complement representation
of -4. However, ComputePHILiveOutRegInfo() would generate a constant
with the upper 16-bits set to zero. The SelectionDAG builder would use
that information to generate an AssertZero node that would remove any
subsequent trunc & zero_extend nodes.

In theory, we should modify ComputePHILiveOutRegInfo() to consult
target-specific hooks about the way they prefer to materialize the
given constants. However, git-blame reports that this specific code
has not been touched since 2011 and it seems to be working well for every
target so far.

Reviewers: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11592

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243636 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-30 11:51:44 +00:00
Nick Lewycky 6fc1adf9c7 Fix typo "fuction" noticed in comments in AssumptionCache.h, and also all the other files that have the same typo. All comments, no functionality change! (Merely a "fuctionality" change.)
Bonus change to remove emacs major mode marker from SystemZMachineFunctionInfo.cpp because emacs already knows it's C++ from the extension. Also fix typo "appeary" in AMDGPUMCAsmInfo.h.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243585 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-29 22:32:47 +00:00
Frederic Riss 2096f62462 [dsymutil] Rename -v option to -verbose
The dsymutil-classic -v option dumps the tool version rather than
putting it in verbose mode. Rename -v to -verbose and update the
tests that use it (in the process removing it from a few tests that
didn't require it anymore since the -dump-debug-map option was
introduced).
A followup commit will reintroduce the -v option that dumps the
version.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243582 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-29 22:29:34 +00:00
Simon Pilgrim f66eda96eb [X86][SSE] Keep 32-bit target i64 vector shifts on SSE unit.
This patch improves the 32-bit target i64 constant matching to detect the shuffle vector splats that are introduced by i64 vector shift vectorization (D8416).

Differential Revision: http://reviews.llvm.org/D11327

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243577 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-29 21:44:27 +00:00
Tim Northover 3614662adb AArch64: use 32-bit MOV rather than UBFX to truncate registers.
It's potentially more efficient on Cyclone, and from the optimization guides &
schedulers looks like it has no effect on Cortex-A53 or A57. In general you'd
expect a MOV to be about the most efficient instruction with its semantics,
even though the official "UXTW" alias is really a UBFX.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243576 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-29 21:34:32 +00:00
Alex Lorenz 81474d36a0 MIR Serialization: Serialize the frame info's save and restore points.
This commit serializes the save and restore machine basic block references from
the machine frame information class.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243575 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-29 21:09:09 +00:00
Simon Pilgrim 5ff91d8781 [X86][SSE] Vectorize i64 ASHR operations
This patch vectorizes the v2i64/v4i64 ASHR shift operations - the last remaining integer vector shifts that are still being transferred to/from the scalar unit to be completed.

Differential Revision: http://reviews.llvm.org/D11439

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243569 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-29 20:31:45 +00:00
Alexey Samsonov 67e53da671 [ASan] Disable dynamic alloca and UAR detection in presence of returns_twice calls.
Summary:
returns_twice (most importantly, setjmp) functions are
optimization-hostile: if local variable is promoted to register, and is
changed between setjmp() and longjmp() calls, this update will be
undone. This is the reason why "man setjmp" advises to mark all these
locals as "volatile".

This can not be enough for ASan, though: when it replaces static alloca
with dynamic one, optionally called if UAR mode is enabled, it adds a
whole lot of SSA values, and computations of local variable addresses,
that can involve virtual registers, and cause unexpected behavior, when
these registers are restored from buffer saved in setjmp.

To fix this, just disable dynamic alloca and UAR tricks whenever we see
a returns_twice call in the function.

Reviewers: rnk

Subscribers: llvm-commits, kcc

Differential Revision: http://reviews.llvm.org/D11495

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243561 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-29 19:36:08 +00:00
Colin LeMahieu 154b3f0725 [llvm-objdump] Merging MachO DumpSections in to FilterSections. Simplifying some predicate logic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243556 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-29 19:08:10 +00:00
Jingyue Wu 7e90f694b6 Roll forward r242871
r242871 missed one place that should be guarded with isPhysicalReg. This patch
fixes that.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243555 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-29 18:59:09 +00:00
Alex Lorenz dd741a8795 MIR Serialization: Serialize the '.cfi_def_cfa' CFI instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243554 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-29 18:57:23 +00:00
Alex Lorenz 0b7483edda MIR Parser: Parse multiple LHS register machine operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243553 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-29 18:51:21 +00:00
Michael Zolotukhin 607fe5bb28 [Unroll] Handle SwitchInst properly.
Previously successor selection was simply wrong.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243545 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-29 18:10:33 +00:00
Michael Zolotukhin 815580fe7a [Unroll] Don't crash when simplified branch condition is undef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243544 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-29 18:10:29 +00:00
Michael Zolotukhin 952e40ff00 Rename test full-unroll-bad-geps.ll to full-unroll-crashers.ll.
No reason to limit it only to GEP-related crashes. More tests are to
come here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243543 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-29 18:10:23 +00:00
Bruno Cardoso Lopes 4e3c7c262b Revert "[PeepholeOptimizer] Look through PHIs to find additional register sources"
Reported to Broke some internal tests: PR24303

This reverts commit r243486.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243540 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-29 17:46:47 +00:00
Colin LeMahieu edbf9d742e [llvm-objdump] Added -j flag to filter sections that are operated on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243526 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-29 15:45:39 +00:00