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876 Commits

Author SHA1 Message Date
Jim Grosbach
c7352f8ca0 ARM optional size suffix for VLDR/VSTR syntax. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144427 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 23:34:43 +00:00
Jim Grosbach
ce485e7f70 ARM allow Q registers in vldm/vstm register lists. 
rdar://9672822

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144407 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-11 21:27:40 +00:00
Jim Grosbach
5402637ff2 Thumb2 parsing for push/pop w/ hi registers in the reglist. 
rdar://10130228.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144331 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 23:17:11 +00:00
Jim Grosbach
1b332860ae Thumb MUL assembly parsing for 3-operand form. 
Get the source register that isn't tied to the destination register correct,
even when the assembly source operand order is backwards.

rdar://10428630

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144322 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 22:10:12 +00:00
Jim Grosbach
ee10ff89a2 ARM assembly parsing for LSR/LSL/ROR(immediate). 
More of rdar://9704684

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144301 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 19:18:01 +00:00
Jim Grosbach
71810ab7c0 ARM assembly parsing for ASR(immediate). 
Start of rdar://9704684

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144293 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-10 16:44:55 +00:00
Jim Grosbach
3c5d6e4df4 Thumb2 assembly parsing STMDB w/ optional .w suffix. 
rdar://10422955


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144242 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-09 23:44:23 +00:00
Benjamin Kramer
70be28a5ad Simplify some uses of utohexstr. 
As a side effect hex is printed lowercase instead of uppercase now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144013 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-11-07 21:00:59 +00:00
Jim Grosbach
89a6337085 Add Thumb2 alias for "mov Rd, #imm" to "mvn Rd, #~imm". 
When '~imm' is encodable as a t2_so_imm but plain 'imm' is not. For example,
  mov r2, #-3
becomes
  mvn r2, #2

rdar://10349224


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143235 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 22:36:30 +00:00
Jim Grosbach
5d0492cfc4 Thumb2 ADD/SUB instructions encoding selection outside IT block. 
Outside an IT block, "add r3, #2" should select a 32-bit wide encoding
rather than generating an error indicating the 16-bit encoding is only
legal in an IT block (outside, the 'S' suffic is required for the 16-bit
encoding).

rdar://10348481


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143201 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 16:57:07 +00:00
Jim Grosbach
c73d73eb88 ARM Allow 'q' registers in VLD/VST vector lists. 
Just treat it as if the constituent D registers where specified.

rdar://10348896

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143167 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-28 00:06:50 +00:00
Jim Grosbach
88484c0030 Thumb2 t2LDMDB[_UPD] assembly parsing to recognize .w suffix. 
rdar://10348844

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143110 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-27 17:33:59 +00:00
Jim Grosbach
036a67d670 Thumb2 t2MVNi assembly parsing to recognize ".w" suffix. 
rdar://10348584


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143108 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-27 17:16:55 +00:00
Jim Grosbach
a581328ceb Thumb2 ldr pc-relative encoding fixes. 
We were parsing label references to the i12 encoding, which isn't right.
They need to go to the pci variant instead.

More of rdar://10348687

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143068 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-26 22:22:01 +00:00
Jim Grosbach
399cdca4d2 ARM assembly parsing and encoding for VLD1 with writeback. 
Four entry register lists.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142882 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-25 00:14:01 +00:00
Jim Grosbach
5921675ff5 ARM assembly parsing and encoding for VLD1 w/ writeback. 
Three entry register list variation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142876 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-24 23:26:05 +00:00
Jim Grosbach
12431329d6 ARM assembly parsing and encoding for VLD1 w/ writeback. 
One and two length register list variants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142861 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-24 22:16:58 +00:00
Jim Grosbach
1028132b90 Update test for r142801. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142806 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-24 17:26:26 +00:00
Jim Grosbach
224180e81b Assembly parsing for 4-register sequential variant of VLD2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142704 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 23:58:57 +00:00
Jim Grosbach
4661d4cac3 Assembly parsing for 2-register sequential variant of VLD2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142691 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 22:21:10 +00:00
Jim Grosbach
b6310316db Assembly parsing for 4-register variant of VLD1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142682 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 20:35:01 +00:00
Jim Grosbach
cdcfa28056 Assembly parsing for 3-register variant of VLD1. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142675 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 20:02:19 +00:00
Jim Grosbach
280dfad489 ARM VLD parsing and encoding. 
Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.

Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142670 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-21 18:54:25 +00:00
Owen Anderson
cd20c58e98 Revert r142618, r142622, and r142624, which were based on an incorrect reading of the ARMv7 docs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142626 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-20 22:23:58 +00:00
Owen Anderson
5096503184 Fix tests for corrected MSR encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142622 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-20 21:53:19 +00:00
Jim Grosbach
6b09c77b7a ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142583 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-20 15:04:25 +00:00
Jim Grosbach
760b46ce18 Tidy up formatting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142582 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-20 14:57:47 +00:00
Jim Grosbach
d0b614754e ARM VTBX (one register) assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142581 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-20 14:48:50 +00:00
Jim Grosbach
2933e4b2e6 Tidy up formatting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142422 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 21:09:01 +00:00
Jim Grosbach
39dc2af7f9 Tidy up formatting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142421 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 21:08:16 +00:00
Jim Grosbach
0487e459e0 Enable more encoded immediate tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142415 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 20:20:51 +00:00
Jim Grosbach
ca8d1842cf More vmov lane testcases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142414 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 20:19:48 +00:00
Jim Grosbach
aead579017 ARM vmla/vmls assembly parsing for the lane index operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142413 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 20:14:56 +00:00
Jim Grosbach
687656c630 ARM vmov assembly parsing for the lane index operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142412 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 20:10:47 +00:00
Jim Grosbach
9120088979 ARM vmla/vmls assembly parsing for the lane index operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142389 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 18:27:07 +00:00
Owen Anderson
e8692ed5a6 Another failing encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142388 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 18:23:03 +00:00
Jim Grosbach
82fa5fc709 Fix NEON mul encoding tests. Wrong file contents previously. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142387 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 18:14:55 +00:00
Jim Grosbach
0a0374018f ARM vqdmulh assembly parsing for the lane index operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142386 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 18:12:09 +00:00
Jim Grosbach
37a3ed21c4 Remove duplicate test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142383 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 18:05:50 +00:00
Jim Grosbach
9e7df4ad5b Tidy up formatting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142382 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 18:05:16 +00:00
Jim Grosbach
970f787a7e ARM vmul assembly parsing for the lane index operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142381 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 18:01:52 +00:00
Jim Grosbach
ec11d2a1b8 Tidy up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142380 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 18:01:09 +00:00
Owen Anderson
aff187a19a Add a few more testcases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142379 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 17:57:31 +00:00
Owen Anderson
de1ff7f552 Add several FIXME cases for ARM encodings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142377 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 17:50:22 +00:00
Jim Grosbach
5e3e811bf6 Tests for 142365. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142368 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 17:23:34 +00:00
Jim Grosbach
4442824614 Tidy up formatting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142367 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 17:22:53 +00:00
Jim Grosbach
f2f5bc60f6 ARM assembly parsing and encoding for VMOV.i64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142356 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 16:18:11 +00:00
Jim Grosbach
6248a546f2 ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142321 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-18 00:22:00 +00:00
Jim Grosbach
7c81013c45 Enable a few more NEON immediate tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142313 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 23:50:19 +00:00
Jim Grosbach
ea46110f57 ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142303 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-10-17 23:09:09 +00:00