Commit Graph

16 Commits

Author SHA1 Message Date
Jim Laskey
47622e3721 Add dwarf register numbering to register data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27081 91177308-0d34-0410-b5e6-96231b3b80d8
2006-03-24 21:15:58 +00:00
Duraid Madina
b0636041c8 fix stack corruption! Previously, 16-byte whole-FP-register stores were
being treated as needing only 8 bytes (though they were 16 byte aligned.)

This should fix a bunch of tests - anyone have any comments, though?

  - in Target.td , SpillSize and SpillAlignment seem dead - is this what
    Size and Alignment do now?
  - in CodeGenRegisters.h/CodeGenTarget.cpp , DeclaredSpillSize and
    DeclaredSpillAlignment seem dead.
  - there are a bunch of comments here and there that don't clearly
    distinguish between 'size' and 'spillsize' etc. hmm.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25644 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-26 09:45:03 +00:00
Duraid Madina
b9bcd18794 fix register corruption! (my god.) r15 is a scratch reg, using that as
a frame pointer is a pretty doofus thing to do. use r5 instead, and
mark it callee-saved, coz that's what it is!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25526 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-23 06:08:46 +00:00
Duraid Madina
362071d7d4 use proper (82-bit) spills/fills when spilling FP regs, so that
divides don't get broken. this fixes obsequi, smg2000, and probably
a bunch of other stuff (tm)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25385 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-17 02:04:52 +00:00
Duraid Madina
a0a11d289d update tablegen files - nothing to see here
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24939 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-22 03:56:03 +00:00
Nate Begeman
6510b22cec Support multiple ValueTypes per RegisterClass, needed for upcoming vector
work.  This change has no effect on generated code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24563 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-01 04:51:06 +00:00
Duraid Madina
a2df2aee81 add F0 and F1 to the FP register class
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24151 91177308-0d34-0410-b5e6-96231b3b80d8
2005-11-02 07:30:39 +00:00
Duraid Madina
f2db9b88da DAG->DAG instruction selection for ia64! "hello world" works, not much else.
use -enable-ia64-dag-isel to turn this on

TODO: delete lowering stuff from the pattern isel
    : get operations on predicate bits working
    : get other bits of pseudocode going
    : use sampo's mulh/mull-using divide-by-constant magic
    : *so* many patterns ("extr", "tbit" and "dep" will be fun :)
    : add FP
    : add a JIT!
    : get it working 100%

in short: this'll be happier in a couple of weeks, but it's here now so
the tester can make me feel guilty sooner.

OTHER: there are a couple of fixes to the pattern isel, in particular
making the linker happy with big blobs of fun like pypy.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24058 91177308-0d34-0410-b5e6-96231b3b80d8
2005-10-28 17:46:35 +00:00
Chris Lattner
ecbce617ca Split RegisterClass 'Methods' into MethodProtos and MethodBodies
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22929 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-19 19:13:20 +00:00
Chris Lattner
cbec3b00bd Put register classes in namespaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22924 91177308-0d34-0410-b5e6-96231b3b80d8
2005-08-19 18:50:46 +00:00
Duraid Madina
e8fd25f5c5 * OK, after changing to use liveIn/liveOut instead of IDEFs,
to avoid redundant mov out3=r44 type instructions, we need to
tell the register allocator the truth about out? registers.

FIXME: unfortunately, since the list of allocatable registers is immutable,
we can't simply 'delete r127' from the allocation order, say, if 'out0' is
used. The only correct thing we can do is have a linear order of regs:

out7, out6 ... out2, out1, out0, r32, r33, r34 ... r126, r127

and slide a 'window' of 96 registers along this line, depending on how many
of the out? regs a function actually uses. The only downside of this is
that the out? registers will be allocated _first_, which makes the
resulting assembly ugly. :( Note this in the README. Hope this gets fixed
soon. :) (note the 3rd person speech there)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21252 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-12 18:42:59 +00:00
Chris Lattner
9c24ba642e Put out* into the allocation order, allowing the register allocator to
coallesce moves into outgoing args.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21249 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-12 15:12:51 +00:00
Duraid Madina
ca494fddcd stop emitting IDEFs for args - change to using liveIn/liveOut
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21247 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-12 14:54:44 +00:00
Duraid Madina
e00e5ded51 ok, the "ia64 has a boatload of registers" joke stopped being funny today ;)
* fix overallocation of integer (stacked) registers: we can't allocate
  registers for local use if they are required as output registers

this fixes 'toast' in the test suite, and all sorts of larger programs
like bzip2 etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21178 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-09 11:53:00 +00:00
Duraid Madina
4ee131ffa8 make sure 'special' registers don't get allocated
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21109 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-06 06:17:54 +00:00
Duraid Madina
9b9d45f60e and so it begins...
PHASE 1: write instruction selector
PHASE 2: ???
PHASE 3: profit!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20652 91177308-0d34-0410-b5e6-96231b3b80d8
2005-03-17 18:17:03 +00:00