Commit Graph

2679 Commits

Author SHA1 Message Date
Anton Korobeynikov
928eb49cae Make processor FUs unique for given itinerary. This extends the limit of 32
FU per CPU arch to 32 per intinerary allowing precise modelling of quite
complex pipelines in the future.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101754 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-18 20:31:01 +00:00
Chris Lattner
f06b859479 silence some -Wmissing-field-initializers warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101690 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-18 03:30:32 +00:00
Dan Gohman
b35798347e Fix a bunch of namespace polution.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101376 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-15 17:08:50 +00:00
Daniel Dunbar
8f10915145 Remove unnecessary uses of <iostream>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101338 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-15 03:47:24 +00:00
Benjamin Kramer
be10811323 EDis: Don't include inttypes.h. We support compilers which don't provide it. It was unused anyways.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101241 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-14 13:56:38 +00:00
Daniel Dunbar
07b3a041b4 Fix -Asserts warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101191 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-13 23:34:11 +00:00
Sean Callanan
9899f70a74 Fixed a nasty layering violation in the edis source
code.  It used to #include the enhanced disassembly
information for the targets it supported straight
out of lib/Target/{X86,ARM,...} but now it uses a
new interface provided by MCDisassembler, and (so
far) implemented by X86 and ARM.

Also removed hacky #define-controlled initialization
of targets in edis.  If clients only want edis to
initialize a limited set of targets, they can set
--enable-targets on the configure command line.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101179 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-13 21:21:57 +00:00
Johnny Chen
1808e4d251 If all the bit positions are not specified; do not decode the instructions.
We are bound to fail!  For proper disassembly, the well-known encoding bits
of the instruction must be fully specified.

This also removes pseudo instructions from considerations of disassembly,
which is a better design and less fragile than the name matchings.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100899 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-09 21:01:02 +00:00
Chris Lattner
21aa347c28 add minix support, patch by Kees van Reeuwijk! PR6797
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100895 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-09 20:45:04 +00:00
Bob Wilson
ec80e2693a Provide versions of the ARM eh_sjlj_setjmp instructions for non-VFP subtargets
such that the non-VFP versions have no implicit defs of VFP registers.
If any callee-saved VFP registers are marked as having been defined, the
prologue/epilogue code will try to save and restore them.
Radar 7770432.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100892 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-09 20:41:18 +00:00
Johnny Chen
e0c74fb1de ARM decoder emitter should print out useful information unconditionally when it
encounters decoding conflicts, instead of wrapping it inside the DEBUG() macro. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100886 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-09 19:31:33 +00:00
Daniel Dunbar
2381379d1d lit: Add support to OneCommandPerFileTest format to take input directory from input path.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100846 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-09 02:15:10 +00:00
Johnny Chen
2d16a67b94 Now that Evan Cheng has fixed the coalescer bug (r100804), the workaround code
to avoid memcpy() call is no longer necessary.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100811 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-08 21:23:54 +00:00
Benjamin Kramer
454c4ce479 Various MSVC warning fixes about truncated 64 bit shifts and const pointers passed to free.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100767 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-08 15:25:57 +00:00
Benjamin Kramer
127dc5e615 Use errs instead of fprintf.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100754 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-08 09:42:29 +00:00
Sean Callanan
8f993b8c24 Added support for ARM disassembly to edis.
I also added a rule to the ARM target's Makefile to
build the ARM-specific instruction information table
for the enhanced disassembler.

I will add the test harness for all this stuff in
a separate commit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100735 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-08 00:48:21 +00:00
Chris Lattner
75361b69f3 rename llvm::llvm_report_error -> llvm::report_fatal_error
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100709 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 22:58:41 +00:00
Chris Lattner
e3a601b648 add newlines at end of files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100706 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 22:54:55 +00:00
Sean Callanan
5edca81626 Fixed a bug where the disassembler would allow an immediate
argument that had to be between 0 and 7 to have any value,
firing an assert later in the AsmPrinter.  Now, the
disassembler rejects instructions with out-of-range values
for that immediate.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100694 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 21:42:19 +00:00
Eric Christopher
72666f2be9 Fix typo and correct comment somewhat.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100691 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 20:58:16 +00:00
Johnny Chen
3c500e6947 Re-enable ARM/Thumb disassembler and add a workaround for a memcpy() call in
ARMDecoderEmitter.cpp, with FIXME comment.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100690 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 20:53:12 +00:00
Anton Korobeynikov
96085a36db Initial support for different kinds of FU reservation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100645 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-07 18:19:32 +00:00
Chris Lattner
4c842dda39 stringref-ize the MemoryBuffer::get apis. This requires
a co-committed clang patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100485 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-05 22:42:30 +00:00
Jakob Stoklund Olesen
fddb7667ca Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field.
When a target instruction wants to set target-specific flags, it should simply
set bits in the TSFlags bit vector defined in the Instruction TableGen class.

This works well because TableGen resolves member references late:

class I : Instruction {
  AddrMode AM = AddrModeNone;
  let TSFlags{3-0} = AM.Value;
}

let AM = AddrMode4 in
def ADD : I;

TSFlags gets the expected bits from AddrMode4 in this example.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100384 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-05 03:10:20 +00:00
Chris Lattner
35c33bd772 change a ton of code to not implicitly use the "O" raw_ostream
member of AsmPrinter.  Instead, pass it in explicitly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100306 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-04 04:47:45 +00:00
Chandler Carruth
1e86e3fb4b Fix a warning in GCC about a pointless typedef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100268 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-03 04:45:24 +00:00
Chandler Carruth
b421640efa Add the new ARMDecodeEmitter to CMake build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100267 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-03 04:36:43 +00:00
Johnny Chen
55f71187a5 Move variable "Bits" declaration/definition into the DEBUG block where its usage
is expected.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100247 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-02 23:13:52 +00:00
Johnny Chen
493a441391 Fixed build warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100244 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-02 22:51:04 +00:00
Johnny Chen
9981814a40 Change from .../Support/DataTypes.h to .../System/DataTypes.h.
(Fix build failure)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100243 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-02 22:41:06 +00:00
Johnny Chen
b68a3ee82a Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen
backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb,
and the disassembler core which invokes the decoder function and builds up the
MCInst based on the decoded Opcode.

Reviewed by Chris Latter and Bob Wilson.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100233 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-02 22:27:38 +00:00
Daniel Dunbar
e09ccab0ce Add a FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100034 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-31 19:14:05 +00:00
Daniel Dunbar
c3681d334a lit: Make sure to close any files we open as part of redirection.
PR6753.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100032 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-31 18:48:43 +00:00
Chris Lattner
283d1ceb57 Switch pattern sorting predicate from stable sort -> sort, it
doesn't need to be stable because the patterns are fully ordered.

Add a first level sort predicate that orders patterns in this
order:  1) scalar integer operations 2) scalar floating point 
3) vector int 4) vector float.  This is a trivial sort on their
top level pattern type so it is nice and transitive.  The
benefit of doing this is that simple integer operations are
much more common than insane vector things and isel was trying
to match the big complex vector patterns before the simple
ones because the complexity of the vector operations was much
higher.  Since they can't both match, it is best (for compile
time) to try the simple integer ones first.

This cuts down the # failed match attempts on real code by
quite a bit, for example, this reduces backtracks on crafty
(as a random example) from 228285 -> 188369.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99797 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-29 02:02:45 +00:00
Chris Lattner
4810736134 revert 99795, as mentioned, it is disabled anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99796 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-29 01:58:15 +00:00
Chris Lattner
a0401249e8 Check in a (disabled) failed attempt to improve the ordering of
patterns within the generated matcher.  This works great except
that the sort fails because the relation defined isn't 
transitive.  I have a much simpler solution coming next, but want
to archive the code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99795 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-29 01:56:19 +00:00
Chris Lattner
48e86dbe29 print the complexity of the pattern being matched in the
comment in the generated table.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99794 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-29 01:40:38 +00:00
Chris Lattner
2a22cdc716 improve type checking of SDNode operand count. This rejects all cases
where an incorrect number of operands is provided to an sdnode instead
of just a few cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99761 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-28 08:48:47 +00:00
Chris Lattner
caa8870fe0 finally remove the immAllOnesV_bc/immAllZerosV_bc patterns
and those derived from them.  These are obnoxious because
they were written as: PatLeaf<(bitconvert).  Not having an
argument was foiling adding better type checking for operand
count matching up with what was required (in this case,
bitconvert always requires an operand!)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99759 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-28 08:43:23 +00:00
Chris Lattner
7a0eb91b4c teach tblgen to allow patterns like (add (i32 (bitconvert (i32 GPR))), 4),
transforming it into (add (i32 GPR), 4).  This allows us to write type
generic multi patterns and have tblgen automatically drop the bitconvert
in the case when the types align.  This allows us to fold an extra load
in the changed testcase.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99756 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-28 08:38:32 +00:00
Chris Lattner
b775b1e20b validate that input sdnodes don't exist in an output pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-28 06:57:56 +00:00
Chris Lattner
c217305f76 eliminate a bunch of code duplication in ParseTreePattern
by rotating it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99746 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-28 06:50:34 +00:00
Chris Lattner
c812261221 SDTCisVT<0, isVoid> is not valid, reject it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99744 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-28 06:04:39 +00:00
Chris Lattner
aa4e3391c8 add an optimized form of OPC_EmitMergeInputChains for the 1, 0 and
1, 1 cases which are by-far the most frequent.  This shrinks the X86
isel table from 77014 -> 74657 bytes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99740 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-28 05:50:16 +00:00
Chris Lattner
b4a52b04bd fix a long standing fixme, which required fixing a bunch of other
issues to get here.  We now trim the result type list of the
CompleteMatch or MorphNodeTo operation to be the same size as the
thing we're matching.  this means that if you match (add GPR, GPR)
with an instruction that produces a normal result and a flag that
we now trim the result in tblgen instead of having to do it 
dynamically.  This exposed a bunch of inconsistencies in result
counting that happened to be getting lucky since the days of the
old isel.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99728 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-27 20:45:15 +00:00
Chris Lattner
0d7952ed5a fix CodeGenTarget::getRegisterVTs to not return the
same vt multiple times for a register.  For example,
ECX is in 5 different i32 reg classes, just return 
1 i32 instead of 5.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99727 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-27 20:32:26 +00:00
Chris Lattner
9414ae5291 hoist some funky logic into CodeGenInstruction
from two places in CodeGenDAGPatterns.cpp, and
use it in DAGISelMatcherGen.cpp instead of using
an incorrect predicate that happened to get lucky
on our current targets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99726 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-27 20:09:24 +00:00
Chris Lattner
0be6fe7139 continue pushing tblgen's support for nodes with multiple
results forward.  We can now handle an instruction that 
produces one implicit def and one result instead of one or
the other when not at the root of the pattern.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99725 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-27 19:15:02 +00:00
Chris Lattner
5d3569e93c fix a bug in my recent patch that increased opcode size to 2 bytes:
the index comments nested under OPC_SwitchOpcode were off by one.
This fixes the comments.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99722 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-27 18:49:33 +00:00
Dan Gohman
f65f294c99 Remove an unnecessary #include.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99714 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-27 16:33:36 +00:00