Vincent Lejeune
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bb25a01d23
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R600: Non vector only instruction can be scheduled on trans unit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189980 91177308-0d34-0410-b5e6-96231b3b80d8
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2013-09-04 19:53:46 +00:00 |
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Tom Stellard
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6b3f6a744a
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Revert "R600: Non vector only instruction can be scheduled on trans unit"
This reverts commit 98ce62780e.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187526 91177308-0d34-0410-b5e6-96231b3b80d8
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2013-07-31 20:43:27 +00:00 |
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Vincent Lejeune
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98ce62780e
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R600: Non vector only instruction can be scheduled on trans unit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187514 91177308-0d34-0410-b5e6-96231b3b80d8
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2013-07-31 19:31:56 +00:00 |
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Vincent Lejeune
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92f24d403f
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R600: Prettier asmPrint of Alu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180956 91177308-0d34-0410-b5e6-96231b3b80d8
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2013-05-02 21:52:30 +00:00 |
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Benjamin Kramer
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1cb47b9afe
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Test case hygiene.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176772 91177308-0d34-0410-b5e6-96231b3b80d8
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2013-03-09 18:25:40 +00:00 |
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Tom Stellard
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f98f2ce29e
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Add R600 backend
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8
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2012-12-11 21:25:42 +00:00 |
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