Chris Lattner
373c458850
fix bugs in push/pop segment support, rdar://8407242
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113422 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 22:13:08 +00:00
Chris Lattner
ba8e81cca2
implement proper support for sysret{,l,q}, rdar://8403907
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113350 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 05:45:34 +00:00
Chris Lattner
ba8cea450f
implement the iret suite of instructions properly,
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fixing rdar://8403974
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113349 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 05:38:31 +00:00
Chris Lattner
a247685b30
fix the encoding of the "jump on *cx" family of instructions,
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rdar://8061602
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113343 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 04:30:51 +00:00
Evan Cheng
dc0b06c815
Remove a dead comment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113259 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-07 20:01:10 +00:00
Chris Lattner
9389b60a03
fix the operand constraints of the immediate form of in/out,
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allowing unsigned 8-bit operands. This fixes rdar://8208481
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113182 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-06 23:29:05 +00:00
Roman Divacky
436c54a186
Redefine LOOP* instructions from I to Ii8PCRel as they take an i8 argument.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113158 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-06 18:43:14 +00:00
Jakob Stoklund Olesen
3061c4442e
Don't call Predicate_* from X86 target.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112921 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-03 00:35:18 +00:00
Anton Korobeynikov
9f7f83b861
Fix nasty mingw32 bug, which e.g. prevented llvm-gcc bootstrap there.
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Mark _alloca call as clobberring EFLAGS, otherwise some DCE might remove
other flags-clobberring stuff (e.g. cmp instructions) occuring after
_alloca call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112034 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-25 07:50:11 +00:00
Chris Lattner
d80c7e1232
Add a new llvm.x86.int intrinsic, allowing access to the
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x86 int and int3 instructions. Patch by Peter Housel!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111831 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-23 19:39:25 +00:00
Chris Lattner
59f8a6a666
fix PR7465, mishandling of lcall and ljmp: intersegment long
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call and jumps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111496 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-19 01:18:43 +00:00
Eric Christopher
c0b2a2018a
Rework how the non-sse2 memory barrier is lowered so that the
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encoding is correct for the built-in assembler.
Based on a patch from Chris.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111083 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-14 21:51:50 +00:00
Eric Christopher
5cb33a384f
Wording.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110618 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-09 22:52:47 +00:00
Eric Christopher
280f96c508
Be a little bit more specific about target for the memory barrier
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instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110360 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-05 18:36:20 +00:00
Eric Christopher
b6729dc0ef
Make x86-64 membarriers work without sse and clean up some of the
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uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110274 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-04 23:03:04 +00:00
Bruno Cardoso Lopes
5b7dab83e9
Fix typo!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109877 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-30 19:41:24 +00:00
Bruno Cardoso Lopes
3c45734274
Temporary hack to let codegen assert or generate poor code in case
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we are using AVX and no AVX version of the desired intruction is present,
this is better for incremental dev (without fallbacks it's easier to spot
what's missing). Not sure this is the best hack thought (we can also disable
all HasSSE* predicates by dinamically marking them 'false' if AVX is present)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109434 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-26 21:01:18 +00:00
Bruno Cardoso Lopes
cdae7e8244
Add x86 CLMUL (Carry-less multiplication) cpu feature
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109206 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-23 01:17:51 +00:00
Bruno Cardoso Lopes
6b7e9168a4
Add complete assembler support for FMA3 instructions, with descriptions and encodings taken from the AVX manual
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109204 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-23 00:54:35 +00:00
Eric Christopher
9a9d275dc7
Custom lower the memory barrier instructions and add support
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for lowering without sse2. Add a couple of new testcases.
Fixes a few libgomp tests and latent bugs. Remove a few todos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109078 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-22 02:48:34 +00:00
Eric Christopher
dab4dac2a0
Pulling out previous patch, must've run the tests in
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the wrong directory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109005 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-21 09:23:56 +00:00
Eric Christopher
87f41370a8
Lower MEMBARRIER on x86 and support processors without SSE2.
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Fixes a pile of libgomp failures in the llvm-gcc testsuite due
to the libcall not existing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109004 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-21 09:05:23 +00:00
Bruno Cardoso Lopes
94143ee625
Add 256-bit vaddsub, vhadd, vhsub, vblend and vdpp instructions!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108769 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19 23:32:44 +00:00
Daniel Dunbar
77e2dd7bb2
X86: Mark JMP{32,64}[mr] as requires 32-bit/64-bit mode. They are the same
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instruction, we only want to allow the one for the current subtarget.
- This also fixes suffix matching for jmp instructions, because it eliminates
the ambiguity between 'jmpl' and 'jmpq'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108746 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19 20:44:16 +00:00
Daniel Dunbar
e4c52a2c41
X86: Mark some tail call pseduo instruction as code gen only.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108684 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19 07:21:04 +00:00
Daniel Dunbar
df4c47be29
X86: Mark In32/64BitMode on LEAVE[64] and SYSEXIT[64].
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108683 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19 07:21:01 +00:00
Daniel Dunbar
cf246b7f0b
X86: Mark MOV.*_{TC,NOREX} instruction as code gen only, they aren't real.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108680 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19 06:14:49 +00:00
Daniel Dunbar
6c2c9a27c5
X86: MOV8o8a, MOV8ao8, etc. are only valid in 32-bit mode.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108679 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19 06:14:44 +00:00
Bruno Cardoso Lopes
e86b01c153
Start the support for AVX instructions with 256-bit %ymm registers. A couple of
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notes:
- The instructions are being added with dummy placeholder patterns using some 256
specifiers, this is not meant to work now, but since there are some multiclasses
generic enough to accept them, when we go for codegen, the stuff will be already
there.
- Add VEX encoding bits to support YMM
- Add MOVUPS and MOVAPS in the first round
- Use "Y" as suffix for those Instructions: MOVUPSYrr, ...
- All AVX instructions in X86InstrSSE.td will move soon to a new X86InstrAVX
file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107996 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 18:27:43 +00:00
Chris Lattner
c5f5626a29
have the mc lowering process handle a few tail call forms, lowering them to
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jumps where possible and turning the TAILCALL marker in the instruction
asm string into a proper comment.
This eliminates a FIXME and is on the path to finishing:
rdar://7639610 - eliminate encoding and asm info for TAILJMPd TAILJMPr TAILJMPn, etc.
However, I can't eliminate the encodings for these instructions because the JIT
still exists and has its own copy of the encoder, sigh.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107946 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 00:49:41 +00:00
Chris Lattner
599b531a96
Change LEA to have 5 operands for its memory operand, just
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like all other instructions, even though a segment is not
allowed. This resolves a bunch of gross hacks in the
encoder and makes LEA more consistent with the rest of the
instruction set.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107934 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-08 23:46:44 +00:00
Chris Lattner
9fc05227a2
Implement the major chunk of PR7195: support for 'callw'
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in the integrated assembler. Still some discussion to be
done.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107825 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-07 22:27:31 +00:00
Eric Christopher
37106afe02
Add a couple more quick comments.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106717 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 02:07:57 +00:00
Eric Christopher
749bb7e2d9
Update according to feedback.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106677 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 20:49:35 +00:00
Nico Weber
50b9efc2a8
Add support for the x86 instructions "pusha" and "popa".
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106671 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 20:00:58 +00:00
Eric Christopher
18ebf74781
Update uses, defs, and comments for darwin tls patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106621 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 08:01:49 +00:00
Eric Christopher
a938cfb13a
Finish ripping isTwoAddress out of X86. Some mindless formatting
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and operand renaming to help.
The giant turn the constraints on and selectively turn it off
should probably be inverted at some point since it's just largely
50/50.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106367 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 00:37:40 +00:00
Eric Christopher
544153653b
Ensure that mov and not lea are used to stick the address into
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the register. While we're at it, make sure it's in the right one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105645 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-08 22:04:25 +00:00
Eric Christopher
30ef0e5658
Add first pass at darwin tls compiler support.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105381 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-03 04:07:48 +00:00
Daniel Dunbar
dcbab9cf5a
AsmMatcher/X86: Mark _REV instructions as "code gen only", they aren't expected
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to be matched.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104757 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 22:21:28 +00:00
Kevin Enderby
b106543592
Fix the x86 move to/from segment register instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104731 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 20:10:45 +00:00
Jakob Stoklund Olesen
3458e9e4df
Rename X86 subregister indices to something shorter.
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Use the tablegen-produced enums.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104493 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 14:48:17 +00:00
Daniel Dunbar
62e4c671b6
MC/X86: Subdivide immediates a bit more, so that we properly recognize immediates based on the width of the target instruction. For example:
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addw $0xFFFF, %ax
should match the same as
addw $-1, %ax
but we used to match it to the longer encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104453 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 21:02:33 +00:00
Daniel Dunbar
54ddf3d9c7
tblgen/AsmMatcher: Change AsmOperandClass to allow a list of superclasses instead of just one.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104452 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 21:02:29 +00:00
Daniel Dunbar
1fe591da3e
X86: Model i64i32imm properly, as a subclass of all immediates.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104272 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 20:20:39 +00:00
Dan Gohman
e5e4ff974d
Fix assembly parsing and encoding of the pushf and popf family of
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instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104231 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 16:16:00 +00:00
Daniel Dunbar
52322e7b8b
MC/X86: Lower TAILCALLd[64] to JMP_1, to allow relaxation and to avoid same
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prefix byte problem as in r104062.
- As a total hack to keep the TAILCALL markers in the output, which some tests depend on, this invents a new TAILJMP_1 instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104120 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 15:26:43 +00:00
Kevin Enderby
c3ce05c594
Fix so "int3" is correctly accepted, added "into" and fixed "int" with an
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argument, like "int $4", to not get an Assertion error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103791 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 19:16:02 +00:00
Dan Gohman
effc8c5269
Set isTerminator on TRAP instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103778 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 16:46:02 +00:00
Dan Gohman
7f357ec6d2
Add mayLoad and mayStore flags to instructions which missed them.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103776 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 16:34:55 +00:00